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#analog-design
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# analog-design
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Anish

07/31/2020, 6:57 PM
What would redundancy implementation look like for a mixed digital/analog design? I'm wondering if there's straightforward ways of designing the chip that would allow integration of analog circuitry but also have it such that in case there is an issue with the analog logic, it doesn't impact the functionality of the digital portion of the design.
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Adrian Freed

07/31/2020, 7:36 PM
@Anish. You could put the analog design on a different power rail to the digital which might take care of certain faults. The tools for simulating and testing a design before you commit are rather good these days. This means that you may want to think about how you are going to learn what went wrong if the analog design doesn’t work. You may want to think at the beginning about probes and internal nodes you might want to reach. Sometimes adding a probe will ruin a design because you want it to go very fast. In this case you might look at breaking the design into pieces so you can test them independently in case the whole thing doesn’t work. For example an opamp is often organized as an OTA and a Buffer. Analog circuits often have bias current sources. You might add an extra current mirror here or there to confirm the bias currents without interfering with the core circuit. If you are designing an LDO to drive the digital core don’t connect it internally. That way if it fails you can substitute an external LDO.
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Anish

07/31/2020, 7:56 PM
@Adrian Freed Thank you for the response! That makes sense - right now I'm looking at doing fairly low-speed signals (generated by a DAC running in the ~hundreds of KHz range) so I don't think probing would cause a problem. The power rail isolation sounds like a good idea, I'll look into that. The digital core itself would be fairly isolated from the analog logic, with the only connectivity being a 32-bit wide digital input and a 32-bit wide digital output, both of which will be muxed with a second communication option in case analog needs to be bypassed. My main concern is ensuring that I can still talk to the digital core even if the custom-built analog portion of the core fails. (Hopefully it should work- with the spice sims and all- but I want to have a backup since the analog stuff is a bit new to me so it would be more experimental.)
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Trevor Clarke

07/31/2020, 8:04 PM
you usually always want separate rails for digital and analog anyway (and separate grounds) as the digital has a nasty tendency to leak noise into your analog circuitry through the grounds
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Anish

07/31/2020, 8:12 PM
Ah ok
Also - how much verification can be done using SPICE simulations / post-routing simulations vs just following best practices and hoping for the best? (specifically with open-source tools only). I.e. how close can I get to a "guarantee" that the analog portion of the chip will work after being taped out?
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Trevor Clarke

07/31/2020, 8:20 PM
Depends on you simulator and the models available. The fets and such should be fully characterized models. If we also get information on variation, temperature effects, etc. then something like Micro-Cap 12 (not open source but free as in beer) can model worst case, manufacture variation, monte carlo, etc. I'm not sure if ngspice or xspice can do some of these more advanced simulations but they can do temperature analysis and such
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ArunAshok

07/31/2020, 9:30 PM
As far as i know, ngspice could do most of the simulations. Though @Tim Edwards has said that monte carlo is missing or being added/investigated. Always the digital and analog rails should be seperated due to noise concerns like @Trevor Clarke said. Maybe for functionality, one can have a single supply. But for performance and good SNR separation is needed. The analog circuitr should be simulated across all corners. Redundant circuits is not applicable as the all circuits are impacted by the process voltage and temperature variations. One can put tuning or digital control such that the parameters could be tuned post fabrication.
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Tim Edwards

07/31/2020, 9:40 PM
@ArunAshok: The monte carlo equations are in the spectre models. I know more or less how to apply them in ngspice, but it is not as straightforward as the rest of the translation from spectre to ngspice format, most of which is just syntactical.
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yrrapt

08/01/2020, 12:24 AM
@Tim Edwards I understand the issues you're having the monte Carlo parameters. However, is there the possibility to release just the nominal spice models sooner to start the design? I don't think people will be targetting six sigma performance for the first tapeout and having a starting point for analogue design would be hugely beneficial
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Tim Edwards

08/01/2020, 12:27 AM
@yrrapt : Oh, absolutely we're getting out the models as fast as we can organize and convert and correct them (which is a lot of work). I'm saving the monte carlo equations in comments so they won't be missing, either.
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yrrapt

08/01/2020, 12:47 AM
@Tim Edwards great, thanks. Excited to get designing