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#analog-design
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# analog-design
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Pepijn de Vos

08/05/2020, 12:14 PM
What are people thinking of building on the analog side? On the digital side probably the RISC-V and retrocomputing people will have a lot of fun, and I suppose they might want some analog peripherals for their SoCs, but I'm curious if people have other grand plans to build cool analog stuff.
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Mike Frank

08/06/2020, 3:10 AM
I'm not sure if you'd even call this "analog," but I am developing a very new style of digital logic that is different enough from conventional digital that existing digital cells & flows are not useful to us at all. So, we have to develop our own cells from the transistors up. Also, our signaling schemes are nonstandard.
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Pepijn de Vos

08/06/2020, 9:02 AM
Whoa, this is extremely fascinating. I was just thinking, are we just going to play catch-up, or will there be actual innovation. Anywhere where I can learn more about this or possibly get involved? I've been toying with some ideas for phase-based logic for sensitive computations.
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Mike Frank

08/06/2020, 4:22 PM
We're preparing an invited overview paper now for ICCD (https://www.iccd-conf.com) and a more detailed technical paper for ICRC (https://icrc.ieee.org/). The current project is building demonstration chips for this logic style called 2LAL (two-level adiabatic logic) that was developed in 2000-2004 at UF but never got to the layout stage due to a lack of funding. Some publications from that early period can be found here (paper, slides) and here (slides). We have a new version of 2LAL that achieves what I call "perfectly adiabatic" computing, which in principle can be orders of magnitude more energy efficient than conventional digital, limited only by leakage.
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Troy Benjegerdes

08/07/2020, 3:55 PM
@Mike Frank can you send me a copy of that paper..
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Mike Frank

08/07/2020, 4:38 PM
@Troy Benjegerdes - The paper I linked is freely downloadable. The IEEExplore publication is not really a paper; it is just printed handouts of the slide deck from a later talk; attaching it to this comment.
The best place to start to find all of my more recent work is My Public Page.
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Jim Swonger

08/07/2020, 5:27 PM
The base process flow looks interesting for POL DC-DC and linear regulators up to 12V (+margin). I am hoping that eventually the sister 60V/120V +LDMOS flows will be migrated to this open PDK as well.