We're preparing an invited overview paper now for ICCD (
https://www.iccd-conf.com) and a more detailed technical paper for ICRC (
https://icrc.ieee.org/). The current project is building demonstration chips for this logic style called 2LAL (two-level adiabatic logic) that was developed in 2000-2004 at UF but never got to the layout stage due to a lack of funding. Some publications from that early period can be found here (
paper,
slides) and here (
slides). We have a new version of 2LAL that achieves what I call "perfectly adiabatic" computing, which in principle can be orders of magnitude more energy efficient than conventional digital, limited only by leakage.