Anyone have experience using magic to extract to a spice model?

IIRC It's fairly straight forward, you just use ext and ext2spice in the tcl command window

I have trouble with resistance and capacitance extraction when the design is hierarchical

oh I see, personally haven't had that problem

@Jon Pry: I assume you're referring to parasitic capacitance and resistance extraction? Parasitic capacitance is just a matter of setting "cthresh" before doing "ext2spice". Parasitic resistance requires a complicated chain of commands using "extract", "ext2sim", "extresist", and "ext2spice extresist on". It has known problems that are due to the lack of information in a .sim file. I intend to rewrite the code to remove the dependence on the ".sim" file, which was an unfortunate decision by someone a long time ago, and completely unnecessary (all needed information is in the .ext file after "extract").

@Tim Edwards I was able to work around those issues when the design was flat. But if I have a top cell that for example wires together some standard cells it all goes sideways. My top cell ends up with no resistors somehow

@Jon Pry: I don't see any contacts in your top level; you have a square of metal1 over the two inverters, but the inverter pins are on local interconnect, and there's no connection between them.

@Tim Edwards you are correct about all those things. i fixed these issues but still cannot get resistance values in the top level cell

I found that I have to do "ext2sim" separately on every file, including the low-level ones. So the list of commands was:

gds read foo
load TOP
extract all
ext2sim labels on
ext2sim
load scs8hs_inv_1
ext2sim
load scs8hs_tap_1
ext2sim
load TOP
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice

The resulting TOP.spice file has "(null)" entries in it which I believe are the substrate and might come from needing to do "set SUB VSS" up top. This is one of the problems having to do with using the sim file format, which has no concept of substrate. If the "set SUB" doesn't work, then it may just require substitution by hand in the file. That's why I want to get rid of that dependency on "ext2sim"; it should fix everything that is currently wrong with the full parasitic extraction.

Hi @Tim Edwards @Jon Pry @Muhammad Arsalan Athar, I was able to generate the extracted netlist but I am not sure how to simulate it ???? because the model names in the extracted netlist is nshort and phighvt, and they are not defined anywhere other than the sky130A.tech file.

You need to import the analog models from the pdk

@Jon Pry Can you please point me to the models that you are referring to?

Ext2spice scale on

Thank You!

@Affan Abbasi: The problem seems to be a very outdated sky130A.tech file. The sky130A.tech file corresponding to the names in the skywater-pdk repo was updated at the same time that the sky130_fd_pr repository was released.

Thanks @Tim Edwards Let me update the tech file then. I'll keep you posted. @Roomi Naqvi @Muhammad Arsalan Athar