@User from your simulation using wrappers for stdcells i got a nice idea implemented in xschem (2 lines of code per netlist format 🙂 ), basically you can specify the 'format=...' string in instance attributes, so overriding symbol's 'format=...' attribute that defines the netlisting syntax. This teoretically allows to simulate directly with sky130 gates without using wrappers. However this requires to specify the 'format=' in all instances, certainly not feasible for normal design activity. It's just handy for testing. By specifying 'format=...' in instance you can change pin order, symbol name etc... see example circuit with xschem.

@Stefan Schippers that's a good idea. However, I'm liking the idea of generating the symbols from the liberty files more and more. But unfortunately I don't have much time to put into doing that.

Of course this is the real good approach , i am also not digging into that since there are people already working on that...

Yes I agree. For now just wrapping the cells is fine for me, until the automated solution is available.

About the rom8k example (512WL x256BL) an interesting and uncommon design feature is that only the bitlines that are being read (16 out of 256) are precharged, saving lot of power (at the expense of some timing performance) on big ROMs. picture shows 3 read accesses pattern '11', '00', '01' on ldq[1:0]; in 3rd read cycle only bitlines 2, 18, 34, ... are precharged... 5.5ns access from clock edge. Precharge time is self-calibrated using a pessimistic dummy bitline (pessimistic means it has all transistors in array connected).

That's great, I'm starting to understand it more and more. I will look at in more detail and maybe ask you some questions about it, if that's ok?

sure no problem