<@U01F94FVBU7> (<@U016HU5HK8V>): I did not want t...
# analog-design
@User (@User): I did not want to have users connect to the ESD-sensitive pin by default. If you must connect to it for some reason, you should be able to route out to it. If not, let me know.
@Tim Edwards the route between our user_project_wrapper and the chip_io is done automaticaly when we run make at the caravel top directory. Should we change any verilog file to change the conections or should we route it manually on the caravel.mag?
Just re-do the route manually after you've done everything you can do with the automatic tools.