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#analog-design
Title
# analog-design
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Stefan Schippers

01/21/2021, 1:01 AM
@User rf models are loaded by default, i can use these transistors. These have fixed dimensions, well defined layouts (fingered layout, lot of contacts, double ended gate contacts). models work however i have strange results, an ac analysis shows current gain dropping to 0db (ft) at ~100MHz, while a transient simulation with a small signal sinusoidal voltage applied to the gate shows a current gain of 15dB (Id/Ig amplitudes) at 10GHz. The standard 01v8_lvt transistor in the same testbench shows perfect coherence between AC and tran simulation, (see a previous post here).
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andagel

02/01/2021, 10:40 PM
Did you find out what was going on? No clue, really, but could it be an artifact due the component values and thus the current in the FET, in turn appearing somewhere in the model expressions for, say, non-linear gate-drain and drain-source capacitance? Or may it be that the drain modulation-induced effects in the model are linearized in AC? Do you still see the discrepancy using finite Q-factor for the passives (some resistance in parallel with C1-L2, and maybe also in series with Cgs1, plus some kind of termination from the gate to gnd, 50Ω each, for instance)? I'm very curious about it: I'll try too see for myself asap, but please share any insight you might have if you can!
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Stefan Schippers

02/02/2021, 11:34 AM
@andagel i have not investigated further. These models are not loaded by default from the toplevel
sky130.lib.spice
file, so my suspect is these are not 'production ready' or not properly ported to ngspice. However this is only my speculation. Will try to have a further look on it.
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