Did you find out what was going on? No clue, really, but could it be an artifact due the component values and thus the current in the FET, in turn appearing somewhere in the model expressions for, say, non-linear gate-drain and drain-source capacitance? Or may it be that the drain modulation-induced effects in the model are linearized in AC? Do you still see the discrepancy using finite Q-factor for the passives (some resistance in parallel with C1-L2, and maybe also in series with Cgs1, plus some kind of termination from the gate to gnd, 50Ω each, for instance)? I'm very curious about it: I'll try too see for myself asap, but please share any insight you might have if you can!