<@U01EK2VDMDG> I did pretty thorough corner analys...
# analog-design
@User I did pretty thorough corner analysis on the bandgap. A little bit on the PLL but I was completing that during the deadline extension so I didn't have much time to do all the verification, just typical- I figured a half verified design on silicon is better than a fully verified design on my hard drive. Especially when I'm not paying for the silicon
@yrrapt same thought on my end.
@yrrapt do we still need to do the patching required for ngspice to work properly?
@Amro Tork I'm not sure to be honest. I think @Stefan Schippers is the most knowledgeable about that
@Amro Tork i thought i answered this, but for some reason it is not here... anyway, i compiled today pre-master branch of ngspice, and still i get param errors, at least on the nfet_g5v0d16v0 when using the original pdk.
Copy code
** ngspice-34+ : Circuit level simulation program
Original line no.: 34, new internal line no.: 14671:
 Formula() error.
      sb_cadfixedvalue_nvhv=1.585; sky130_fd_pr__nfet_g5v0d16v0__rdiff_tc2=7.824000e-006; sky130_fd_pr__nfet_g5v0d16v0__rdiff_tc1=1.483000e-003; sky130_fd_pr__nfet_g5v0d16v0__rdiff=5.906500e+003; mult=1; sd=0; sb=0; sa=0; m=1; mf=1; delvto=0; l=0.7; w=5.0; ad=int((nf+1)/2)*w/nf*0.29; as=int((nf+2)/2)*w/nf*0.29; pd=2*int((nf+1)/2)*(w/nf+0.29); ps=2*int((nf+2)/2)*(w/nf+0.29); nrd=0.29/w; nrs=0.29/w;
Original line no.: 0, new internal line no.: 16535:
Undefined number [as]
Thanks for the clarification @Stefan Schippers I think my question was before you sent your answer. I really appreciate your help. It’s always appreciated.