Matt Venn
03/05/2021, 11:06 AMStefan Schippers
03/06/2021, 11:44 PM.subckt sky130_fd_sc_hd__conb_1 LO HI VPB VNB VGND VPWR
R0 HI VPWR 0.01
R1 VGND LO 0.01
.ends
@mehdi solution to use a voltage source might be even better :
.subckt sky130_fd_sc_hd__conb_1 LO HI VPB VNB VGND VPWR
V0 HI VPWR 0
V1 VGND LO 0
.ends
VVactive Vactive 0 0
instead of:
Vactive VGND 0 0
the above just creates another voltage source on the VGND node that is paralled with the other one:
Vgnd VGND 0 0
a loop of voltage sources creates a singular matrix.
This fix allows me to simulate your design:XFILLER_94_361 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_67_586 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_27_428 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_82_556 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_52_18 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_22_166 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_77_317 VPWR VGND VPWR VGND sky130_fd_sc_hd__decap_8
XFILLER_77_306 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_4
XFILLER_58_520 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_73_501 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_4
XFILLER_45_269 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_26_483 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_60_239 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_9_159 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
XFILLER_3_89 VPWR VGND VPWR VGND sky130_fd_sc_hd__decap_8
XFILLER_95_147 VGND VPWR VPWR VGND sky130_fd_sc_hd__decap_12
X_1270_ _1404_/A _1270_/HI VPWR VGND VGND VPWR sky130_fd_sc_hd__conb_1
Matt Venn
03/07/2021, 9:32 AMStefan Schippers
03/07/2021, 3:27 PMsky130_fd_sc_hd__conb_1
subcircuit definition in wrapped_seven_segment.spice.complete
, since you are correctly including the modified resistor.spice
version.
• Ensure you have a .spiceinit
file in the directory where you launch ngspice (or in your home directory) with the following one-liner in it: set ngbehavior=hs
. This sets the right compatibility mode for library parsing (hspice like) and also correctly handle the wnflag
option.
• For some reason the antenna subcircuit incorrectly netlists the diode as a subcircuit:
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VPWR VPB VNB
X0 VNB DIODE sky130_fd_pr__diode_pw2nd_05v5 area=4.347e+11p
.ends
You need to replace the 'X0' with 'D0':
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VPWR VPB VNB
D0 VNB DIODE sky130_fd_pr__diode_pw2nd_05v5 area=4.347e+11p
.ends
With these changes ngspice loads the netlist without errors (it prints some warning about unrecognized parameters in antenna diode model, but that is not critical at all).
It is still running, will post the results (if any) asap.Trying gmin = 1.0000E-12 Note: One successful gmin step
Note: One successful source step
Supplies reduced to 0.1000% Warning: singular matrix: check nodes la_data_in[6] and la_data_in[6]
Supplies reduced to 0.0000% Warning: singular matrix: check nodes la_data_in[6] and la_data_in[6]
Warning: source stepping failed
Transient solution failed -
this is probably because there are so many undriven input nodes....
Try to insert the required input node drivers by using a script, for example:
...
...
vla_data_in[6] la_data_in[6] 0 0
vla_data_in[7] la_data_in[7] 0 0
...
...
I don't know what are the best values (low or high) for these inputs...Matt Venn
03/07/2021, 4:58 PMStefan Schippers
03/07/2021, 6:13 PM******
** ngspice-34+ : Circuit level simulation program
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Copyright 2001-2020, The ngspice team.
** Please get your ngspice manual from <http://ngspice.sourceforge.net/docs.html>
** Please file your bug-reports at <http://ngspice.sourceforge.net/bugrep.html>
** Creation Date: Mon Feb 15 18:29:32 UTC 2021
******
some time ago a fix was made to reduce memory consumption, for some reason a mos model was loaded in memory for every mos instance, while ideally one mos model should be loaded per transistor type. This makes a huge difference in some cases.
ngspic euses lot of ram on skywater pdk. this is a problem both for ngspice and the way the pdk is set up, however i have only 4GB of physical ram and the simulation process never went above 1GB virtual ram, which is still a lot but manageable.Matt Venn
03/07/2021, 6:14 PMStefan Schippers
03/07/2021, 6:16 PMMatt Venn
03/07/2021, 6:17 PMStefan Schippers
03/07/2021, 6:24 PMMatt Venn
03/07/2021, 6:43 PMStefan Schippers
03/07/2021, 6:44 PMresistor.spice, wrapped_seven_segment.spice.complete, inputs.spice,
all the Xtest
instance lines, add this line:
X0 VPWR VPWR 0 0 sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u
This adds a single nmos transistor with gate and drain connected to power.
Try to simulate this. If that fails there is something fundamentally broken .Matt Venn
03/07/2021, 7:03 PMStefan Schippers
03/07/2021, 7:05 PMMatt Venn
03/07/2021, 7:06 PMStefan Schippers
03/07/2021, 7:07 PMMatt Venn
03/07/2021, 7:08 PMStefan Schippers
03/07/2021, 7:12 PM.lib "/path/to/pdk/models/sky130.lib_tt.spice" tt
to get all models recognized...
******* SkyWater sky130 model library *********
* Typical corner (tt)
.lib tt
* MOSFET
.include "../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__tt.corner.spice"
.include "../cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__tt.corner.spice"
.include "../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__tt.corner.spice"
.include "../cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__tt.corner.spice"
.include "../cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__tt.corner.spice"
.include "../cells/esd_nfet_01v8/sky130_fd_pr__esd_nfet_01v8__tt.corner.spice"
.include "../cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__tt.corner.spice"
.include "../cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__tt.corner.spice"
.include "../cells/esd_pfet_g5v0d10v5/sky130_fd_pr__esd_pfet_g5v0d10v5__tt.corner.spice"
.include "../cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__tt.corner.spice"
.include "../cells/pfet_g5v0d16v0/sky130_fd_pr__pfet_g5v0d16v0__tt.corner.spice"
.include "../cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__tt.corner.spice"
.include "../cells/nfet_g5v0d16v0/sky130_fd_pr__nfet_g5v0d16v0__tt_discrete.corner.spice"
.include "../cells/esd_nfet_g5v0d10v5/sky130_fd_pr__esd_nfet_g5v0d10v5__tt.corner.spice"
.include "corners/tt/nonfet.spice"
* Mismatch parameters
.include "../cells/nfet_01v8/sky130_fd_pr__nfet_01v8__mismatch.corner.spice"
.include "../cells/pfet_01v8/sky130_fd_pr__pfet_01v8__mismatch.corner.spice"
.include "../cells/nfet_01v8_lvt/sky130_fd_pr__nfet_01v8_lvt__mismatch.corner.spice"
.include "../cells/pfet_01v8_lvt/sky130_fd_pr__pfet_01v8_lvt__mismatch.corner.spice"
.include "../cells/pfet_01v8_hvt/sky130_fd_pr__pfet_01v8_hvt__mismatch.corner.spice"
.include "../cells/nfet_g5v0d10v5/sky130_fd_pr__nfet_g5v0d10v5__mismatch.corner.spice"
.include "../cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5__mismatch.corner.spice"
.include "../cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__mismatch.corner.spice"
.include "../cells/nfet_03v3_nvt/sky130_fd_pr__nfet_03v3_nvt__mismatch.corner.spice"
* Resistor/Capacitor
.include "r+c/res_typical__cap_typical.spice"
.include "r+c/res_typical__cap_typical__lin.spice"
* Special cells
.include "corners/tt/specialized_cells.spice"
* All models
.include "all.spice"
* Corner
.include "corners/tt/rf.spice"
.endl
Matt Venn
03/07/2021, 7:20 PMStefan Schippers
03/07/2021, 7:25 PMMatt Venn
03/07/2021, 7:27 PMStefan Schippers
03/07/2021, 7:27 PMMatt Venn
03/07/2021, 7:28 PMStefan Schippers
03/07/2021, 7:28 PMMatt Venn
03/07/2021, 7:36 PMStefan Schippers
03/07/2021, 7:37 PMMatt Venn
03/07/2021, 7:37 PMStefan Schippers
03/07/2021, 7:38 PMMatt Venn
03/07/2021, 7:49 PMStefan Schippers
03/09/2021, 9:29 AM