Could I get some help with a spice simulation I have extract

Question

Could I get some help with a spice simulation I have extracted a netlist from a small design hardened with OpenLANE Now I want to measure the maximum current it draws in one clock cycle I ve put my work so far in this repo <https github com mattvenn simulate 7seg>

Stefan Schippers · Answer

< Matt Venn> when simulating a subcircuit in spice you should at the very least connect input nodes usually landing to gates of MOS transistors to something like 0 GND VGND for low level or VPWR your VCC level for high level Output nodes of a subcircuit can be left unconnected An unconnected mos gate usually leads to a singular matrix A simulator can not find a DC solution for that node voltage While a digital simulator simply assigns X or U to such nodes an analog transistor level simulator needs to be able to find a numerical solution for these voltage values

Stefan Schippers · Answer

< Matt Venn> for the missing res generic po this is a missing model I got past this error by replacing the tier cell as follows ` subckt sky130 fd sc hd conb 1 LO HI VPB VNB VGND VPWR` `R0 HI VPWR 0 01` `R1 VGND LO 0 01` ` ends` < mehdi> solution to use a voltage source might be even better ` subckt sky130 fd sc hd conb 1 LO HI VPB VNB VGND VPWR` `V0 HI VPWR 0` `V1 VGND LO 0` ` ends`

Stefan Schippers · Answer

< Matt Venn> First of all disregard my first post ngspice is able to add low conductances to gnd to floating gate nodes to avoid singularities Unfortunately i can not edit or delete that post if i understand correctly you want to set the Vactive input node to logic level low 0V The correct syntax is the following `VVactive Vactive 0 0` instead of `Vactive VGND 0 0` the above just creates another voltage source on the VGND node that is paralled with the other one `Vgnd VGND 0 0` a loop of voltage sources creates a singular matrix This fix allows me to simulate your design

Stefan Schippers · Answer

reducing tran step to 1p eliminates numerical oscillations in waveform

Stefan Schippers · Answer

< Matt Venn> your wrapped seven segment spice contains just decap cells and the above mentioned tier cell current is extremely low as there is no cmos circuitry inside it ```XFILLER 94 361 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 67 586 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 27 428 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 82 556 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 52 18 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 22 166 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 77 317 VPWR VGND VPWR VGND sky130 fd sc hd decap 8 XFILLER 77 306 VGND VPWR VPWR VGND sky130 fd sc hd decap 4 XFILLER 58 520 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 73 501 VGND VPWR VPWR VGND sky130 fd sc hd decap 4 XFILLER 45 269 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 26 483 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 60 239 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 9 159 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 XFILLER 3 89 VPWR VGND VPWR VGND sky130 fd sc hd decap 8 XFILLER 95 147 VGND VPWR VPWR VGND sky130 fd sc hd decap 12 X 1270 1404 A 1270 HI VPWR VGND VGND VPWR sky130 fd sc hd conb 1```

Matt Venn · Answer

Thanks so much Stefan I still make such rookie mistakes with spice

Matt Venn · Answer

Yes I deleted most of the contents of the model to make iteration faster

Matt Venn · Answer

The full model is also in the repo with a complete extension

Matt Venn · Answer

I ll check it myself later

Matt Venn · Answer

OK I ve made those changes and now I do get a result but it s just a flat line

Matt Venn · Answer

I still get a lot of these errors

Matt Venn · Answer

image png

Matt Venn · Answer

I pushed your suggested fixes to the repo Could you pull and run on your side I think maybe I have a library setup issue

Matt Venn · Answer

though I have done other simulations of standard cells successfully

Stefan Schippers · Answer

< Matt Venn> trying now

Stefan Schippers · Answer

< Matt Venn> i am simulating your testbench I commented the `sky130 fd sc hd conb 1` subcircuit definition in `wrapped seven segment spice complete` since you are correctly including the modified `resistor spice` version Ensure you have a ` spiceinit` file in the directory where you launch ngspice or in your home directory with the following one liner in it `set ngbehavior=hs` This sets the right compatibility mode for library parsing hspice like and also correctly handle the `wnflag` option For some reason the antenna subcircuit incorrectly netlists the diode as a subcircuit ``` subckt sky130 fd sc hd diode 2 DIODE VGND VPWR VPB VNB X0 VNB DIODE sky130 fd pr diode pw2nd 05v5 area=4 347e+11p ends``` You need to replace the X0 with D0 ``` subckt sky130 fd sc hd diode 2 DIODE VGND VPWR VPB VNB D0 VNB DIODE sky130 fd pr diode pw2nd 05v5 area=4 347e+11p ends``` With these changes ngspice loads the netlist without errors it prints some warning about unrecognized parameters in antenna diode model but that is not critical at all It is still running will post the results if any asap

Stefan Schippers · Answer

< Matt Venn> at the end ngspice was unable to find an initial solution for the transient simulation ```Trying gmin = 1 0000E 12 Note One successful gmin step Note One successful source step Supplies reduced to 0 1000 Warning singular matrix check nodes la data in 6 and la data in 6 Supplies reduced to 0 0000 Warning singular matrix check nodes la data in 6 and la data in 6 Warning source stepping failed Transient solution failed ``` this is probably because there are so many undriven input nodes Try to insert the required input node drivers by using a script for example vla data in 6 la data in 6 0 0 vla data in 7 la data in 7 0 0 I don t know what are the best values low or high for these inputs

Matt Venn · Answer

Mine gets killed after the system runs out of memory 24GB

Matt Venn · Answer

I reduced sim time to 500p with resolution of 1p and that doesn t help

Matt Venn · Answer

I ve made the changes you suggested added a python script to generate unused inputs and pushed

Matt Venn · Answer

still unable to simulate due to running out of ram

Stefan Schippers · Answer

< Matt Venn> what version of ngspice are you using i have this compiled from the pre master ngspice git branch ``` ngspice 34+ Circuit level simulation program The U C Berkeley CAD Group Copyright 1985 1994 Regents of the University of California Copyright 2001 2020 The ngspice team Please get your ngspice manual from Please file your bug reports at Creation Date Mon Feb 15 18 29 32 UTC 2021 ``` some time ago a fix was made to reduce memory consumption for some reason a mos model was loaded in memory for every mos instance while ideally one mos model should be loaded per transistor type This makes a huge difference in some cases ngspic euses lot of ram on skywater pdk this is a problem both for ngspice and the way the pdk is set up however i have only 4GB of physical ram and the simulation process never went above 1GB virtual ram which is still a lot but manageable

Matt Venn · Answer

27 grimacing grimacing

Stefan Schippers · Answer

ok so the advice is to update ngspice from sources D

Matt Venn · Answer

Ok will fo

Matt Venn · Answer

Btw do you know how to just do a simple DC current measurement

Stefan Schippers · Answer

< Matt Venn> i think the most straightforward way is to insert following instruction into your control section measure tran avg current AVG i Vdd from=0 to=2n you can also insert it outside of the control block by adding a dot measure tran avg current AVG i Vdd from=0 to=2n where avg curent is a tag to be used in the output printout AVG is the operator average in this case i Vdd is the variable in this case current thru Vdd from and to set the time interval

Matt Venn · Answer

Thanks Stefan

Matt Venn · Answer

I ve updated to 34 now

Matt Venn · Answer

and getting a lot of these

Stefan Schippers · Answer

crss fingers slightly smiling face

Stefan Schippers · Answer

oh thats weird

Stefan Schippers · Answer

Try to comment out the includes for `resistor spice wrapped seven segment spice complete inputs spice ` all the `Xtest` instance lines add this line `X0 VPWR VPWR 0 0 sky130 fd pr nfet 01v8 ad=0p pd=0u as=0p ps=0u w=650000u l=150000u` This adds a single nmos transistor with gate and drain connected to power Try to simulate this If that fails there is something fundamentally broken

Matt Venn · Answer

image png

Matt Venn · Answer

I ve just tried one of my other simulations and that works fine

Matt Venn · Answer

so I ll try to work out the difference

Stefan Schippers · Answer

Just to be sure comment these inc sky130 fd pr cells pfet 01v8 hvt sky130 fd pr pfet 01v8 hvt tt pm3 spice inc sky130 fd pr cells nfet 01v8 sky130 fd pr nfet 01v8 tt pm3 spice inc sky130 fd pr models sky130 fd pr model r+c model spice The sky130 fd pr models sky130 lib spice should be enough I don t think this will change the result but just to be sure

Matt Venn · Answer

yes with all those commented out it doesn t have all theose errors

Stefan Schippers · Answer

some of the above includes are supposed to be called from the top level lib file may be including from a global context clashes some definitions

Matt Venn · Answer

then I try to simulate again the 7seg and get model not found errors again

Matt Venn · Answer

image png

Matt Venn · Answer

I ve had that before with scale issues

Matt Venn · Answer

I wonder if the extracted spice scale is not matching

Stefan Schippers · Answer

i have created a sky130 lib tt spice in the models directory of the skywater pdk that looks like this it contains only the tt corner to speed up parsing i only do a ` lib path to pdk models sky130 lib tt spice tt` to get all models recognized ``` SkyWater sky130 model library Typical corner tt lib tt MOSFET include cells nfet 01v8 sky130 fd pr nfet 01v8 tt corner spice include cells nfet 01v8 lvt sky130 fd pr nfet 01v8 lvt tt corner spice include cells pfet 01v8 sky130 fd pr pfet 01v8 tt corner spice include cells nfet 03v3 nvt sky130 fd pr nfet 03v3 nvt tt corner spice include cells nfet 05v0 nvt sky130 fd pr nfet 05v0 nvt tt corner spice include cells esd nfet 01v8 sky130 fd pr esd nfet 01v8 tt corner spice include cells pfet 01v8 lvt sky130 fd pr pfet 01v8 lvt tt corner spice include cells pfet 01v8 hvt sky130 fd pr pfet 01v8 hvt tt corner spice include cells esd pfet g5v0d10v5 sky130 fd pr esd pfet g5v0d10v5 tt corner spice include cells pfet g5v0d10v5 sky130 fd pr pfet g5v0d10v5 tt corner spice include cells pfet g5v0d16v0 sky130 fd pr pfet g5v0d16v0 tt corner spice include cells nfet g5v0d10v5 sky130 fd pr nfet g5v0d10v5 tt corner spice include cells nfet g5v0d16v0 sky130 fd pr nfet g5v0d16v0 tt discrete corner spice include cells esd nfet g5v0d10v5 sky130 fd pr esd nfet g5v0d10v5 tt corner spice include corners tt nonfet spice Mismatch parameters include cells nfet 01v8 sky130 fd pr nfet 01v8 mismatch corner spice include cells pfet 01v8 sky130 fd pr pfet 01v8 mismatch corner spice include cells nfet 01v8 lvt sky130 fd pr nfet 01v8 lvt mismatch corner spice include cells pfet 01v8 lvt sky130 fd pr pfet 01v8 lvt mismatch corner spice include cells pfet 01v8 hvt sky130 fd pr pfet 01v8 hvt mismatch corner spice include cells nfet g5v0d10v5 sky130 fd pr nfet g5v0d10v5 mismatch corner spice include cells pfet g5v0d10v5 sky130 fd pr pfet g5v0d10v5 mismatch corner spice include cells nfet 05v0 nvt sky130 fd pr nfet 05v0 nvt mismatch corner spice include cells nfet 03v3 nvt sky130 fd pr nfet 03v3 nvt mismatch corner spice Resistor Capacitor include r+c res typical cap typical spice include r+c res typical cap typical lin spice Special cells include corners tt specialized cells spice All models include all spice Corner include corners tt rf spice endl```

Stefan Schippers · Answer

since the top lib file uses relative paths cells you should call a lib file that is placed inside models

Matt Venn · Answer

tried that same error messages as when I include the normal lib

Matt Venn · Answer

re my scale idea I don t think that s it because the scale of the fets dimensions looks the same as the simulations I have that work

Matt Venn · Answer

could you do a fresh clone of my repo with recursive to get the models as I have them And tell me if you get the same issue now I m on ngspice34

Matt Venn · Answer

hash is c98a3fc64cebe002b19c8cc816db0d0b7828bea7

Stefan Schippers · Answer

so it is a git clone recursive <https github com mattvenn simulate 7seg git>

Stefan Schippers · Answer

working

Matt Venn · Answer

yep

Stefan Schippers · Answer

you probably did not checkin inputs spice it is missing

Matt Venn · Answer

make should make it

Matt Venn · Answer

make sim

Stefan Schippers · Answer

ah sorry doing

Stefan Schippers · Answer

yes with your git cloned i get the same unfound models

Stefan Schippers · Answer

now trying with my local skywater pdk

Stefan Schippers · Answer

yes with a single replacement of your lib with my lib lib home schippes skywater pdk libraries sky130 fd pr latest models sky130 lib tt spice tt simulation goes straight to the end You should comment out the sky130 fd sc hd conb 1 subckt since it is overidden by the resistor spice include Just to remove a warning

Stefan Schippers · Answer

so there are some differences in the pdk files

Matt Venn · Answer

ok

Matt Venn · Answer

thanks a lot Stefan

Matt Venn · Answer

I think this will get me there I m on my laptop with an outdated pdk so I ll check this all on my work pc tomorrow and use your include file

Matt Venn · Answer

looks like that will speed up sim too

Stefan Schippers · Answer

try to get a new fresh copy of the pdk i think that will fix the boat

Matt Venn · Answer

yeah I m trying v0 9 openlane and have the relevent pdk so will check it tmorrow and post back

Stefan Schippers · Answer

by experience i know everything is rapidly evolving a 2 months old is considered old here hehehe while 2 months is in no case enough to get any software packaged for a linux distro gt so any packaged eda software is outdated by definition slightly smiling face

Stefan Schippers · Answer

I hve crushed my head against the pdk many times while creating the xschem symbol libraries for skywater It s a slowly convergent trial amp error amp refine process

Stefan Schippers · Answer

since there are many actors involved the pdk itself the simulator xschem and many other tools Not to mention a digital flow slightly smiling face i think you had your pile of issues

Matt Venn · Answer

Yep But gratifying to get results

Matt Venn · Answer

Stefan

Matt Venn · Answer

I don t have anything in skywater pdk libraries sky130 fd pr latest

Matt Venn · Answer

I ve installed the pdk with openlane by running make pdk

Matt Venn · Answer

is there something else I have to do to get the models

Matt Venn · Answer

no whoops I was looking in the wrong lib

Matt Venn · Answer

I needed to do git submodule update libraries sky130 fd pr latest in skywater pdk

Matt Venn · Answer

current png

Matt Venn · Answer

Thanks Stefan

Matt Venn · Answer

have updated my repo with instructions

Matt Venn · Answer

Stefan Schippers · Answer

muscle