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#analog-design
Title
# analog-design
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Varun Majji

04/15/2021, 6:44 AM
is there any way i can simulate both analog ips and a microprocessor functionality together in any simulation software.like if i want to do it in ngspice it will definitely crash,also verilog simulators cant be used for analog,is there any software which combines both
k

Kunal

04/15/2021, 7:24 AM
There was a "cheap" way we did it by defining all analog signals as "real" valued in verilog, and used iverilog to simulate. Other than that, not sure, if there's anything open-source available for mixed-signal simulations @Tim Edwards can give more comments on this
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Pepijn de Vos

04/15/2021, 7:53 AM
Currently sky130 does not work with xyce though. And ngspice has "internal" cosimulation where they don't have an external interface, but have a way to simulate digital models. It's still quite slow though.
You can tell yosys to synthesize to generic cells, write to spice, and use this spice library to simulate as digital models in ngspice https://gist.github.com/pepijndevos/2f41507b821b9a3db65beb68d3330b3b
That's for sure orders of magnitude faster than a full analog simulation of the whole CPU, but still a lot slower than a digital simulator.
t

Tim Edwards

04/15/2021, 2:21 PM
There are scripts in the qflow distribution that convert from verilog to SPICE and XSPICE, but @Pepijn de Vos has a method that is more direct. Both ways are equivalent. The method @Kunal mentioned that I was using is just a way to do digital simulation with iverilog while including the analog components---but it is not an analog simulation, because the analog components are replaced by very simple behavioral models. But it is good for a functional simulation to make sure that the digital core is correctly driving the analog control signals. The other method I know of is a bit difficult to work with, but there's a branch of ngspice with the "d_hdl" XSPICE primitive that will run iverilog as a cosimulator communicating with ngspice through an input/output pipe. The main problem with it is that iverilog is the top-level process that launches ngspice, so it can have only one iverilog process running. If there are multiple digital blocks that need to be simulated (including digital core + testbench verilog, which counts as two modules), then you have to write a wrapper module around the whole thing. It is similar to the ghdl cosim mentioned above, using the VPI interface to launch ngspice and communicate with it.