There are scripts in the qflow distribution that convert from verilog to SPICE and XSPICE, but @Pepijn de Vos has a method that is more direct. Both ways are equivalent. The method @Kunal mentioned that I was using is just a way to do digital simulation with iverilog while including the analog components---but it is not an analog simulation, because the analog components are replaced by very simple behavioral models. But it is good for a functional simulation to make sure that the digital core is correctly driving the analog control signals. The other method I know of is a bit difficult to work with, but there's a branch of ngspice with the "d_hdl" XSPICE primitive that will run iverilog as a cosimulator communicating with ngspice through an input/output pipe. The main problem with it is that iverilog is the top-level process that launches ngspice, so it can have only one iverilog process running. If there are multiple digital blocks that need to be simulated (including digital core + testbench verilog, which counts as two modules), then you have to write a wrapper module around the whole thing. It is similar to the ghdl cosim mentioned above, using the VPI interface to launch ngspice and communicate with it.