Tim Edwards
04/23/2021, 1:17 AMsky130_ef_io__analog_pad
which now installs from the custom section of open_pdks. It is basically what I suggested, which is a power pad with the clamp circuit yanked out of it, and all metal removed from around the pad except for the pad ring busses. I threw a deep nwell under the whole thing for good measure. I have no idea if it will meet the 5GHz bandwidth requirement, but it is as much as I can do with relatively simple edits.Can Wang
04/24/2021, 8:13 AMlvs_pad.spice
) from magic layout reports zero nodes. In this netlist, the pad was recognized as a min cap. Does this look correct to you? Or maybe I am doing something wrong... Please let me know if you think somethin is wrong. Thanks!.mag
file.Tim Edwards
04/24/2021, 6:33 PMCan Wang
04/24/2021, 11:51 PMTim Edwards
04/25/2021, 2:15 PMCan Wang
04/25/2021, 6:50 PMEXT
file, all ports are set. However, port in
disappears when I execute ext2spice -o
. I think it might be because some of the setting I used to extract netlist is wrong. For extraction, I basically run extract all
, ext2spice lvs
and ext2spice -o ./lvs.spice
. From what I am seeing, magic merge port in
to port P_CORE
, then P_CORE
is merged into a internal port of m3_xxx
, which is one node of a resistor. Given all that, in the extracted netlist, there are no metal resistor and port in & P_CORE
. Do you think the extraction step I used looks correct? ThanksTim Edwards
04/26/2021, 2:33 AMCan Wang
04/26/2021, 3:34 AMTim Edwards
04/26/2021, 1:38 PMCan Wang
04/26/2021, 2:10 PMout
. I will redo the pin label and delete the extra m5 and try it again.😃@Tim EdwardsTim Edwards
04/26/2021, 2:13 PMCan Wang
04/26/2021, 2:16 PMport make
the labels.in
pin in my extraction results still merges with some internal nodes of pad_and_busses subcell. I've also checked original power pad, it looks like there is no rmetal 5 layer.( I've drawn a rmetal 5 on the side for reference) However, I noticed that when I read the gds, there are several sub-cells missing. I tried reload the latest tech file and it didn't work. Could you give some hints on this issue? Thanks!Tim Edwards
04/28/2021, 1:22 PMCan Wang
04/28/2021, 1:27 PMTim Edwards
04/28/2021, 1:31 PMCan Wang
04/28/2021, 1:38 PMTim Edwards
04/28/2021, 1:42 PMCan Wang
04/28/2021, 1:47 PMP_CORE
and observe the output at P_PAD
. A 3-dB bandwidth of ~16 GHz is observed. It should be enough for most of the applications in sky130. For your record, most of the parasitic comes from the overlap between P_CORE
and VSS/VDD
(pad ring metal structure).Tim Edwards
05/03/2021, 9:20 PMCan Wang
05/04/2021, 4:38 AM