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#analog-design
Title
# analog-design
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Amro Tork

05/06/2021, 8:37 AM
I was hoping to ask you all if you can take a look and may be provide your feedback.
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J. Scott Elder

05/06/2021, 11:41 AM
Link is broken.
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Amro Tork

05/06/2021, 12:34 PM
@J. Scott Elder Sorry forgot to make it public.
It's public now.
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Luis Henrique Rodovalho

05/06/2021, 1:51 PM
The OTAs should not be made with 1.8 V transistors, since VDD will be higher than that. You should use the nfet_g5v and pfet_g5v devices.
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J. Scott Elder

05/06/2021, 1:54 PM
So the 1.8V models work out to 3V like they are 3V-capable transistors?
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Luis Henrique Rodovalho

05/06/2021, 2:02 PM
The NMOS input Miller OTA transistor sizing is a bit odd. You should not mix different width transistors to mirror currents, as transistors with different sizes have different properties, such as Vt. You should use M7 6 X 12/0.5 um and M6 12 X 7.2/0.5 um.
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Amro Tork

05/06/2021, 2:04 PM
@Luis Henrique Rodovalho and @J. Scott Elder Thanks for the feedback.
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Luis Henrique Rodovalho

05/06/2021, 2:04 PM
The PMOS input OTA connections are wrong. The current mirror input, transistor M6, which is biased by the Ibias terminal, should be in diode configuration (gate and drain short-circuited). The output PMOS transistor M7 is connected as diode.
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Amro Tork

05/06/2021, 2:05 PM
@Eslam Morsie Could you please address the comment above?
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Luis Henrique Rodovalho

05/06/2021, 2:07 PM
I'm experienced with other PDKs, such as TSMC 0.18. They have pmos2v and pmos3v, for example. pmos2v is for the 1.8 V core transistors and pmos3v is for 3.3 V. The main difference between them is the oxide thickness. I guess its the same thing for this PDK.
A nfet_g5v0d10v5 device seems to have maximum 5 V for VGS and 10.5 V for its VDS. I'm not sure, but it seems so.
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Amro Tork

05/06/2021, 2:20 PM
@J. Scott Elder That's fundamentally wrong. We should use 3V or 5V NMOS
@Eslam Morsie Could you please help change this?
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J. Scott Elder

05/06/2021, 2:24 PM
@Luis Henrique Rodovalho You are correct. The process has 5v gate oxide, but Vds breakdown can be engineered beyond 5v. This is typical for all manufacturers.
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Amro Tork

05/06/2021, 2:28 PM
@J. Scott Elder and @Luis Henrique Rodovalho, @Eslam Morsie is Junior Analog Designer working with us. I'm depending on the community here to help guide him with issues that he faces.
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J. Scott Elder

05/06/2021, 2:38 PM
@Amro Tork It is important for a learning engineer to first understand what is modeled and what is not modeled before constructing circuits. Without that knowledge, impractical circuits can be designed, simulated, but fail months after silicon comes back. This is one reason why analog IC design is so hard. But this is also why I don't consider the open PDK to be adequate. Industry standard PDKs include very accurate models that show real world effects like breakdown. And they include model features that mimic breakdowns. Throw error flags if the designer uses them in dangerous ways; like using a 1.8V transistor in a 3V circuit.
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Amro Tork

05/06/2021, 2:44 PM
@J. Scott Elder That falls on me. Unfortunately, I'm full time IC Design consultant and that what we do as a company. I should have given him more time. And at least taken a closer look on which transistor his using. Skywaters work is considered as place for training our future consultants a good area to play and learn for experienced designers like yourself. Unfortunately, I give more attention to revenue generating work.
@J. Scott Elder all foundries provide SOA with the models that would through an error with high voltage.
I was discussing that earlier with @Eslam Morsie to run SOA. But didn't check even if we have it in the model or not.
@Luis Henrique Rodovalho the higher voltage transistors usually reflect thicker gates oxide or different High-K material as you have mentioned. I don't believe in this technology they are using any of the High-K materials.
@J. Scott Elder I actually highlighted that designing using those models would be extremely difficult because it lacks many things earlier before even the first shuttle. But I got a feedback that the main strength behind open source community is that people kind of help each other.
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J. Scott Elder

05/06/2021, 2:49 PM
I think it would be a great project for a beginning engineer to run iv curves and breakdown stress curves on all the pdk devices. See what is modelled, what is not. Do the results follow textbook expected performance? Even as an expert analog engineer, that is the first thing I do when starting a first design with a new process where I don't have experience.
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Amro Tork

05/06/2021, 2:50 PM
At one point in the previous run, someone helped us with a basic design of VCO over an inductor that we have taped out in the last shuttle. Hoping that we could characterize it and later build some RF circuits later.
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@J. Scott Elder It doesn't
That was my very initial conclusion. And I opened a PR early on the model cards for skywater-pdk release.
That was the first thing and most probably the only thing that I have done myself.
@J. Scott Elder I have to say that I had some weird experiences before with commercial foundries. But the thing when we face those issues, I send them feedback and we get it fixed.
But here we rely on the community.
TSMC is by far the best foundry in almost everything and the level of details provided. If your entire experience is with them, then please lower your expectation.
@J. Scott Elder I'm still hoping that we could build real working silicon with this process. So please don't lose faith. 🙂
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J. Scott Elder

05/06/2021, 2:56 PM
I read on slack about lots of engineers just jumping in and designing. Implicitly they are assuming the models are accurate. Several engineers have posted simulation results using the models that show they can't be accurate. IC design is not like software design. When writing open source code everyone uses a guaranteed compiler. So if the code doesn't run, the first thing suspected is the code, not the compiler. And feedback is immediate. Here, a designer must have the same level of trust on the models because it takes months to see if a design works.
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Amro Tork

05/06/2021, 2:58 PM
Well, I don't trust the simulation results even with commercial tools or commercial foundries based on my experience.
The methodology that we are trying to do differently here is that we widen our variance (Corners + MC) above what you normally do with the commercial tools and relay on the community experts like yourself to do review and get feedback.
I insist that we publish the simulation for corners for our designs for that reason.
I might even extend the sigma on the corner itself manually by changing the actual dimensions of the transistors.
I would say what just happened is our first Community based Design Review has just been done. And looking for more iterations.
I was trying to convince the people here instead of making separate projects. May be focus on a single big design and harness all the engineering talents here and split it among the people here. Let Juniors learn and experienced designers review and confirm.
But unfortunately, I never got the community to agree on this.
It would allow efficient use of all people time.
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Luis Henrique Rodovalho

05/06/2021, 3:09 PM
You are using this topology. It's not recommended for CMOS design, because it's using resistive loads.
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Amro Tork

05/06/2021, 3:09 PM
@Luis Henrique Rodovalho Recommendations?
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Luis Henrique Rodovalho

05/06/2021, 3:09 PM
Instead, you should use something like this. Use active loads.
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Amro Tork

05/06/2021, 3:10 PM
Ok
Good point.
@Eslam Morsie Could you please address this?
@Luis Henrique Rodovalho I think your concern is Area right?
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Luis Henrique Rodovalho

05/06/2021, 3:15 PM
The concern is that integrated resistors are bad. They show more process variability than transistors. They should be avoided as much as possible. And, if there is active load, the OTA output does not need to provide current.
In the first design, the OTA output is connected to the resistors. In the second bandgap reference circuit, the OTA is connected to the PMOS transistors gate, so no output current is needed.
This way, the OTA output stage transistors can be made smaller and use less current.
Here, the LDO OTA uses a ideal current source. The bandgap itself can provide the bias current. You just need to mirror the bandgap active load.
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Amro Tork

05/06/2021, 3:22 PM
@Luis Henrique Rodovalho process variability could be addressed by properly interleaving the 2 resistors in the layout?
@Luis Henrique Rodovalho Will give the second topology a run.
@Luis Henrique Rodovalho @Eslam Morsie is actively working now on replacing the Ideal current source.
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Luis Henrique Rodovalho

05/06/2021, 3:27 PM
There is mismatch process variability and global process variability. Global process variability can't be addressed without some kind of calibration. Mismatch can be only minimized by using larger devices. The thing is that resistor global and local mismatch is worse than for transistors, so you need more area.
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Amro Tork

05/06/2021, 3:28 PM
@Luis Henrique Rodovalho Ok
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Luis Henrique Rodovalho

05/06/2021, 3:29 PM
The bandgap voltage reference can double as a current reference. There is no need for a second current source.
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Amro Tork

05/06/2021, 3:33 PM
Thanks @Luis Henrique Rodovalho
Appreciate all the feedback.
I think @Eslam Morsie should be able to address most of it soon.
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J. Scott Elder

05/06/2021, 3:52 PM
@Luis Henrique Rodovalho @Amro Tork The original architecture has superior PSRR because VDD does not enter into the first stage. I wouldn't be so quick to dismiss it.
@Luis Henrique Rodovalho @Amro Tork The original architecture is also lower noise. Very low frequency 1/f for resistors. And the op amp input stage can be bipolar transistors, which also have very low 1/f corners.
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Amro Tork

05/06/2021, 4:38 PM
@User I had the same concern about noise. But I don’t consider myself expert in Bandgap design. Usually designers go to resistance for 2 reasons noise and linearity. Flicker noise here is important as we are designing near DC.
@Eslam Morsie could work on both versions and see which is better
also he could give the BJT input Bandgap design a go as well.
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J. Scott Elder

05/06/2021, 4:41 PM
@Amro Tork Paul Brokaw is the inventor of the bandgap. Here is his bandgap design book. It tells you almost all you need to know. https://www.renesas.com/us/en/document/whp/how-make-bandgap-voltage-reference-one-easy-lesson-paul-brokaw
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Luis Henrique Rodovalho

05/06/2021, 4:59 PM
@J. Scott Elder recommended reference, by Brokaw, has this circuit. As you can see, the OTA is biased by the bandgap reference itself. It should be good enough for a LDO. Now, 1/f noise can be an issue. It depends on the LDO specs you're designing.
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Kunal

05/06/2021, 5:03 PM
@sherylcorina @Swarup Pulujkar - Lot of learnings about your bandgap IP in this thread. So adding both of you
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J. Scott Elder

05/06/2021, 5:04 PM
What is good enough depends upon the objective. As you point out, noise can be an issue. I also believe PSRR is an issue. I'm not suggesting your proposed circuit is wrong. Rather I am saying that the original architecture has benefits as well.
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Amro Tork

05/06/2021, 5:30 PM
@J. Scott Elder @Eslam Morsie did literature review I believe. And he picked this based on the idea that it’s the simplest and it should be good enough for driving digital circuitry. And that’s our plan at least for this tapeout.
@J. Scott Elder Eslam is working on changing the OTA design inside the LDO to improving the PSRR. I told him to use either Folded Cascode or telescopic cascode.
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Luis Henrique Rodovalho

05/06/2021, 5:38 PM
I don't know exactly how is your LDO testbench. What did you use as load? A resistor? An ideal current source? What are the specs?
The buffer transistor, M1, is extremely large. 1000 X 60/0.5 um
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Amro Tork

05/06/2021, 6:00 PM
I asked to try to reach similar performance to this one
@Eslam Morsie could you please answer Luis questions?
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Luis Henrique Rodovalho

05/06/2021, 7:01 PM
This TI LDO can output 300 mA for a 3.3 V output. For an 1.8 V output voltage, it is equivalent to a load resistance RL 1.8/0.3 = 6 Ohm. It is a lot of power! A ATmega328P draws 1.5 mA, for example. And the TI LDO is a discrete component. In the end, I don't know which application is your target.
Disclaimer: I'm just a graduate student with experience in ultra-low-voltage basic analog blocks. System level circuits are far away from my area of expertise.
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J. Scott Elder

05/06/2021, 7:07 PM
@Amro Tork If you'd like help, here is my suggestion. Post a specification that you seek to achieve. That is the first step for any engineer designing any circuit. With the specification, people can be more efficient with their comments. Take an LDO specification from a manufacturer and markup their data sheet. Then run your circuit under the test conditions specified in the data sheet.
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Eslam Morsie

05/06/2021, 8:48 PM
@Luis Henrique Rodovalho I made two designs of the OTA ine with supply voltage 1.8v using 1.8 transistors and another one with supply voltage 5v with 5v transistors I only demonstrate the one with 1.8v supply the two designs are in OTA folder.
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Amro Tork

05/06/2021, 8:51 PM
@Eslam Morsie please use 5V transistors for 1.8V output LDO
The input voltage is higher than 5V
@Eslam Morsie you will need to change the design
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Eslam Morsie

05/06/2021, 8:55 PM
@Amro Tork ok
@Amro Tork I am marking all the notes now
@Luis Henrique Rodovalho @J. Scott Elder I marked all your notes and I appreciate your suggestions. Many thanks.
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Amro Tork

05/06/2021, 9:27 PM
@Luis Henrique Rodovalho and @J. Scott Elder My ultimate target to complete 2 main chips. MCU like the ATmega328p, I’m focusing on the RISC-V architecture right now. The other chip would be SDR/Transceiver. Last tapeout we taped out several inductor designs to characterize the the RF specs of the process including the substrate. And thankfully our tapeout was accepted. I don’t think I can work on the RF side this iteration due to resources limitation. I’m focusing on SOC chip that is based on RISC-V architecture. The TI LDO is good for both the RF and SOC applications. But it’s overkill for SOC design. Unfortunately I’m not full time on this and I didn’t do power budgeting and actually I didn’t derive the specs. When I shared TI design with Eslam I told him to focus on 6 main specs from this datasheet: • PSRR • Quiescent Current • Dropout Voltage • Output Noise • Input Voltage Range Referred to our technology supply voltage. • Line regulation The rest doesn’t matter that much. Like output current. To be honest it falls on me again. I should have done power budgeting to make sure what the output current requirements to derive the circuit.
I actually think using the Atmega328p as guidence because for this time out I want to tapeout the SOC. We could use the electrical specs for that MCU as reference.
The RF stuff will wait for the upcoming tapeout run.
I’ll summarize the specs in our Git repo that we are targeting and we will share that with you mostly by tomorrow my time.
@J. Scott Elder @Luis Henrique Rodovalho I would really appreciate your feedback after that.
@J. Scott Elder and @Luis Henrique Rodovalho does that sound like a plan for you?
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Luis Henrique Rodovalho

05/06/2021, 9:46 PM
System design is actually harder than designing a LDO. I'm sure that you and your team can design a LDO that just works, but a LDO that works within the specifications is another matter. The LVS and DRC checks can be bigger problems than designing and simulating and we don't have enough experience with the open source analog design flow yet. I can try to help, but, remember, I'm just a graduate student and I'm just begining to learn how to work with this PDK.
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J. Scott Elder

05/06/2021, 10:07 PM
@Amro Tork I'm happy to look over specifications and schematics.
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Amro Tork

05/06/2021, 10:13 PM
@Luis Henrique Rodovalho I have more than 15 years in the chip design consultancy. My main areas of strength are Physical Verification, Layout, On chip RF design, Analog design specially for ultra low supply filters, switched capacitor circuits, Analog layout, Analog design automation on all simulation tools. I participated in many tapeouts. My main problem is that I don’t have much time for this. I didn’t work in the power management domain except once. All our consulting services we provide to our client is based on Commercial tools.
@J. Scott Elder that would be really helpful.
@Luis Henrique Rodovalho Based on my experience in this domain. We can’t achieve a realistic outcome each one of us as a community is working in his/her isolated Island. I’m hoping that one day we could get something like like a Raspberry Pi designed by the community. This needs collaboration and divide and conquer strategy and allocation to different teams to get a realistic outcome.
I could give you a small example. The team that works on a premium power management chip is about 30 to 70 engineers for example. Including layout engineers, analog designers, digital verification engineers, digital design engineers, esd engineers, etc... And many other roles to achieve that target. Thankfully efabless is trying to do the heavy lifting and completing many of those roles. But there are many gaps that needs to be filled.
Keep in mind that engineers are dedicated for that chip only. And they all collaborate for that single target.
Interesting publication
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Luis Henrique Rodovalho

05/07/2021, 6:46 PM
https://github.com/lhrodovalho/sky130_ldo.git This is a very simple LDO circuit for the SKY130 PDK. It's just a spice netlist. There are no circuit diagrams nor layouts. Not even documentation. I hope it it can be useful.
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Amro Tork

05/07/2021, 7:04 PM
Thanks @Luis Henrique Rodovalho
👍
Specs?
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Luis Henrique Rodovalho

05/07/2021, 7:25 PM
PSRR: 60 dB @ 10 kHz. 1kOhm load. Works above 2.6 V VDD
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Amro Tork

05/07/2021, 7:26 PM
@Luis Henrique Rodovalho Did you so stability analysis and IC conditions?
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Luis Henrique Rodovalho

05/07/2021, 7:26 PM
For a smaller load, it should work with a lower VDD.
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Amro Tork

05/07/2021, 7:28 PM
Vdropout?
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Luis Henrique Rodovalho

05/07/2021, 7:29 PM
I didn't use two stage OTAs, only single stage symmetrical OTA using composite transistors to improve gain. The OTAs are stable because they are single stage, so they have 90° phase margin. I guess the system is stable.
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Amro Tork

05/07/2021, 7:29 PM
Vdropout?
Max supply current?
• PSRR • Quiescent Current • Dropout Voltage • Output Noise • Input Voltage Range Referred to our technology supply voltage. • Line regulation
We need these specs
Across corners
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Luis Henrique Rodovalho

05/07/2021, 7:39 PM
About 13 mV dropout, comparing the output voltage for 1 GOhm and 1 KOhm loads.
The output voltage falls from 1.821 to 1.818 by decreasing the VDD from 3.3 to 2.6 V, for 1 kOhm load. 0.23%/V, if my calculations are right. I still haven't simulated for corners. The voltage range must decrease for lower temperature and slow corners.
There a lot of room for improvement, in special for the buffer transistor dimensions. It is just a 16 X 3 um/ 0.5 um PMOS. If you want it to drive a smaller resistive load, you can increase the output transistor total width. Now its driving a 1.8 mA load.
https://sbmicro.org.br/sforum-eventos/sforum2009/colombo.pdf http://www.lci.ufsc.br/pdf/_00309905.pdf There is the documentation. The opamps' topology is symmetrical OTA with PMOS input biased by the bandgap itself. The transistors in the schematic uses trapezoidal arrays to increase gain. It's not supposed to be the final version. Just a template. It still needs a start-up circuit to guarantee it will work properly. The transient simulation seems good, as it has a stable output. I haven't simulated noise, but, if it is a problem, you can increase the transistor dimensions accordingly.
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J. Scott Elder

05/07/2021, 10:42 PM
My recollection is the LDO should drive a switching load. If that is the case, a moderately large capacitor will be required at the output. If no capacitor is required at the load, then an op amp would work. I didn't see a capacitor in the test bench. Generally, a load capacitor greatly complicates the loop compensation.
Also, it is important in an LDO design to check the load step response. When the LDO is powering low voltage logic, it would not be acceptable to have a 100mV over or undershoot.
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Luis Henrique Rodovalho

05/08/2021, 12:55 AM
A 1 kHz square wave current load with 1 mA amplitude on top of a 1 kOhm charge. It has no capacitive load. Typical corner at room temperature. It seems stable as overshoot is minimal.
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J. Scott Elder

05/08/2021, 1:00 AM
You should try a 0A to full scale load step in 5ns. Similar to a processor transitioning from sleep to wake. Without a load capacitor, the phase margin won't be affected. Similar to an opamp.
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Luis Henrique Rodovalho

05/08/2021, 3:07 PM
100 pF + 1Gohm load + 1 mA switching current load with 5 ns rise time.
Without the capacitive load it's a bit better. No ringing.
Yet, I had to make some modifications in the design. It was an oscillator! Without any load, for a 100 ps simulation time step, the output oscillates! I had to place a miller capacitor between the drain and gate terminals of the transistor at LDO output stage, and now it is stable.
This is the output using a 10 pF Miller capacitor to stabilize the output.
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J. Scott Elder

05/08/2021, 3:43 PM
Now you’re starting to see the difference between a simple op amp and a voltage regulator. Try to do the same thing with a real load of 100mA when the headroom is 100mv. And to have a competitive design you need to use a pass transistor that is smaller than the competitor’s design so you sell lots of them and make a profit.
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Luis Henrique Rodovalho

05/08/2021, 4:43 PM
It needs a 800 mV headroom (2.6 V VDD) for a 1.8 mA load. It is far from competitive. Anyway, it should be good enough for the die digital core. I guess that the metal wire can withstand 1 mA/um width for electromigration alone, so 100 mA would be too much for the Caravel system. A RF system with power amplifiers would need more.
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J. Scott Elder

05/08/2021, 4:59 PM
It's not clear if it is sufficient because no one has published the requirements in rote detail. While the average load might be 1ma, that doesn't mean the peak load is only 1ma. I see this open-pdk initiative as mostly learning. There isn't enough information in the PDK to do challenging design work. So I've been following along only to offer my comments and insite to help those that are learning. I think you'd be hard pressed to find textbook quality circuits in chips sold on the open market. There are lots of hidden tricks and challenges necessary to economically and reliably solve real problems, and those aren't openly published because it is the secret sauce of commercial companies. BTW, I don't know if you picked up on a very important thing you shared earlier. Namely, SPICE, any SPICE, is just a calculator. It answers only questions you ask. If you don't ask all the questions, or ask them in the right way, you run the risk of spending months waiting to see that what was designed doesn't work. In this case, it was having SPICE show you in the time domain that the circuit was not stable. This is where having a good mentor network is important. People who will help you identify all the questions that need to be asked on SPICE, help make sure the models capture all the important aspects so the simulation results are valid, etc. etc. Good luck Luis. I'm going to step aside from this thread now.
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Juan Andres

05/03/2023, 2:47 AM
Hi, how can I to do this ?