I was hoping to ask you all if you can take a look and may be provide your feedback.

Link is broken.

@J. Scott Elder Sorry forgot to make it public.

The OTAs should not be made with 1.8 V transistors, since VDD will be higher than that. You should use the nfet_g5v and pfet_g5v devices.

So the 1.8V models work out to 3V like they are 3V-capable transistors?

The NMOS input Miller OTA transistor sizing is a bit odd. You should not mix different width transistors to mirror currents, as transistors with different sizes have different properties, such as Vt. You should use M7 6 X 12/0.5 um and M6 12 X 7.2/0.5 um.

@Luis Henrique Rodovalho and @J. Scott Elder Thanks for the feedback.

The PMOS input OTA connections are wrong. The current mirror input, transistor M6, which is biased by the Ibias terminal, should be in diode configuration (gate and drain short-circuited). The output PMOS transistor M7 is connected as diode.

@Eslam Morsie Could you please address the comment above?

I'm experienced with other PDKs, such as TSMC 0.18. They have pmos2v and pmos3v, for example. pmos2v is for the 1.8 V core transistors and pmos3v is for 3.3 V. The main difference between them is the oxide thickness. I guess its the same thing for this PDK.

@J. Scott Elder That's fundamentally wrong. We should use 3V or 5V NMOS

@Luis Henrique Rodovalho You are correct. The process has 5v gate oxide, but Vds breakdown can be engineered beyond 5v. This is typical for all manufacturers.

@J. Scott Elder and @Luis Henrique Rodovalho, @Eslam Morsie is Junior Analog Designer working with us. I'm depending on the community here to help guide him with issues that he faces.

@Amro Tork It is important for a learning engineer to first understand what is modeled and what is not modeled before constructing circuits. Without that knowledge, impractical circuits can be designed, simulated, but fail months after silicon comes back. This is one reason why analog IC design is so hard. But this is also why I don't consider the open PDK to be adequate. Industry standard PDKs include very accurate models that show real world effects like breakdown. And they include model features that mimic breakdowns. Throw error flags if the designer uses them in dangerous ways; like using a 1.8V transistor in a 3V circuit.

@J. Scott Elder That falls on me. Unfortunately, I'm full time IC Design consultant and that what we do as a company. I should have given him more time. And at least taken a closer look on which transistor his using. Skywaters work is considered as place for training our future consultants a good area to play and learn for experienced designers like yourself. Unfortunately, I give more attention to revenue generating work.

I think it would be a great project for a beginning engineer to run iv curves and breakdown stress curves on all the pdk devices. See what is modelled, what is not. Do the results follow textbook expected performance? Even as an expert analog engineer, that is the first thing I do when starting a first design with a new process where I don't have experience.

At one point in the previous run, someone helped us with a basic design of VCO over an inductor that we have taped out in the last shuttle. Hoping that we could characterize it and later build some RF circuits later.

I read on slack about lots of engineers just jumping in and designing. Implicitly they are assuming the models are accurate. Several engineers have posted simulation results using the models that show they can't be accurate. IC design is not like software design. When writing open source code everyone uses a guaranteed compiler. So if the code doesn't run, the first thing suspected is the code, not the compiler. And feedback is immediate. Here, a designer must have the same level of trust on the models because it takes months to see if a design works.

Well, I don't trust the simulation results even with commercial tools or commercial foundries based on my experience.

You are using this topology. It's not recommended for CMOS design, because it's using resistive loads.

@Luis Henrique Rodovalho Recommendations?

Instead, you should use something like this. Use active loads.

Ok

The concern is that integrated resistors are bad. They show more process variability than transistors. They should be avoided as much as possible. And, if there is active load, the OTA output does not need to provide current.

@Luis Henrique Rodovalho process variability could be addressed by properly interleaving the 2 resistors in the layout?

There is mismatch process variability and global process variability. Global process variability can't be addressed without some kind of calibration. Mismatch can be only minimized by using larger devices. The thing is that resistor global and local mismatch is worse than for transistors, so you need more area.

@Luis Henrique Rodovalho Ok

The bandgap voltage reference can double as a current reference. There is no need for a second current source.

Thanks @Luis Henrique Rodovalho

@Luis Henrique Rodovalho @Amro Tork The original architecture has superior PSRR because VDD does not enter into the first stage. I wouldn't be so quick to dismiss it.

@User I had the same concern about noise. But I don’t consider myself expert in Bandgap design. Usually designers go to resistance for 2 reasons noise and linearity. Flicker noise here is important as we are designing near DC.

@Amro Tork Paul Brokaw is the inventor of the bandgap. Here is his bandgap design book. It tells you almost all you need to know. https://www.renesas.com/us/en/document/whp/how-make-bandgap-voltage-reference-one-easy-lesson-paul-brokaw

@J. Scott Elder recommended reference, by Brokaw, has this circuit. As you can see, the OTA is biased by the bandgap reference itself. It should be good enough for a LDO. Now, 1/f noise can be an issue. It depends on the LDO specs you're designing.

@sherylcorina @Swarup Pulujkar - Lot of learnings about your bandgap IP in this thread. So adding both of you

What is good enough depends upon the objective. As you point out, noise can be an issue. I also believe PSRR is an issue. I'm not suggesting your proposed circuit is wrong. Rather I am saying that the original architecture has benefits as well.

@J. Scott Elder @Eslam Morsie did literature review I believe. And he picked this based on the idea that it’s the simplest and it should be good enough for driving digital circuitry. And that’s our plan at least for this tapeout.

I don't know exactly how is your LDO testbench. What did you use as load? A resistor? An ideal current source? What are the specs?

I asked to try to reach similar performance to this one

This TI LDO can output 300 mA for a 3.3 V output. For an 1.8 V output voltage, it is equivalent to a load resistance RL 1.8/0.3 = 6 Ohm. It is a lot of power! A ATmega328P draws 1.5 mA, for example. And the TI LDO is a discrete component. In the end, I don't know which application is your target.

@Amro Tork If you'd like help, here is my suggestion. Post a specification that you seek to achieve. That is the first step for any engineer designing any circuit. With the specification, people can be more efficient with their comments. Take an LDO specification from a manufacturer and markup their data sheet. Then run your circuit under the test conditions specified in the data sheet.

@Luis Henrique Rodovalho I made two designs of the OTA ine with supply voltage 1.8v using 1.8 transistors and another one with supply voltage 5v with 5v transistors I only demonstrate the one with 1.8v supply the two designs are in OTA folder.

@Eslam Morsie please use 5V transistors for 1.8V output LDO

@Amro Tork ok

@Luis Henrique Rodovalho and @J. Scott Elder My ultimate target to complete 2 main chips. MCU like the ATmega328p, I’m focusing on the RISC-V architecture right now. The other chip would be SDR/Transceiver. Last tapeout we taped out several inductor designs to characterize the the RF specs of the process including the substrate. And thankfully our tapeout was accepted. I don’t think I can work on the RF side this iteration due to resources limitation. I’m focusing on SOC chip that is based on RISC-V architecture. The TI LDO is good for both the RF and SOC applications. But it’s overkill for SOC design. Unfortunately I’m not full time on this and I didn’t do power budgeting and actually I didn’t derive the specs. When I shared TI design with Eslam I told him to focus on 6 main specs from this datasheet: • PSRR • Quiescent Current • Dropout Voltage • Output Noise • Input Voltage Range Referred to our technology supply voltage. • Line regulation The rest doesn’t matter that much. Like output current. To be honest it falls on me again. I should have done power budgeting to make sure what the output current requirements to derive the circuit.

System design is actually harder than designing a LDO. I'm sure that you and your team can design a LDO that just works, but a LDO that works within the specifications is another matter. The LVS and DRC checks can be bigger problems than designing and simulating and we don't have enough experience with the open source analog design flow yet. I can try to help, but, remember, I'm just a graduate student and I'm just begining to learn how to work with this PDK.

@Amro Tork I'm happy to look over specifications and schematics.

@Luis Henrique Rodovalho I have more than 15 years in the chip design consultancy. My main areas of strength are Physical Verification, Layout, On chip RF design, Analog design specially for ultra low supply filters, switched capacitor circuits, Analog layout, Analog design automation on all simulation tools. I participated in many tapeouts. My main problem is that I don’t have much time for this. I didn’t work in the power management domain except once. All our consulting services we provide to our client is based on Commercial tools.

https://github.com/lhrodovalho/sky130_ldo.git This is a very simple LDO circuit for the SKY130 PDK. It's just a spice netlist. There are no circuit diagrams nor layouts. Not even documentation. I hope it it can be useful.

Thanks @Luis Henrique Rodovalho

PSRR: 60 dB @ 10 kHz. 1kOhm load. Works above 2.6 V VDD

@Luis Henrique Rodovalho Did you so stability analysis and IC conditions?

For a smaller load, it should work with a lower VDD.

Vdropout?

I didn't use two stage OTAs, only single stage symmetrical OTA using composite transistors to improve gain. The OTAs are stable because they are single stage, so they have 90° phase margin. I guess the system is stable.

Vdropout?

About 13 mV dropout, comparing the output voltage for 1 GOhm and 1 KOhm loads.

My recollection is the LDO should drive a switching load. If that is the case, a moderately large capacitor will be required at the output. If no capacitor is required at the load, then an op amp would work. I didn't see a capacitor in the test bench. Generally, a load capacitor greatly complicates the loop compensation.

A 1 kHz square wave current load with 1 mA amplitude on top of a 1 kOhm charge. It has no capacitive load. Typical corner at room temperature. It seems stable as overshoot is minimal.

You should try a 0A to full scale load step in 5ns. Similar to a processor transitioning from sleep to wake. Without a load capacitor, the phase margin won't be affected. Similar to an opamp.

100 pF + 1Gohm load + 1 mA switching current load with 5 ns rise time.

Now you’re starting to see the difference between a simple op amp and a voltage regulator. Try to do the same thing with a real load of 100mA when the headroom is 100mv. And to have a competitive design you need to use a pass transistor that is smaller than the competitor’s design so you sell lots of them and make a profit.

It needs a 800 mV headroom (2.6 V VDD) for a 1.8 mA load. It is far from competitive. Anyway, it should be good enough for the die digital core. I guess that the metal wire can withstand 1 mA/um width for electromigration alone, so 100 mA would be too much for the Caravel system. A RF system with power amplifiers would need more.

It's not clear if it is sufficient because no one has published the requirements in rote detail. While the average load might be 1ma, that doesn't mean the peak load is only 1ma. I see this open-pdk initiative as mostly learning. There isn't enough information in the PDK to do challenging design work. So I've been following along only to offer my comments and insite to help those that are learning. I think you'd be hard pressed to find textbook quality circuits in chips sold on the open market. There are lots of hidden tricks and challenges necessary to economically and reliably solve real problems, and those aren't openly published because it is the secret sauce of commercial companies. BTW, I don't know if you picked up on a very important thing you shared earlier. Namely, SPICE, any SPICE, is just a calculator. It answers only questions you ask. If you don't ask all the questions, or ask them in the right way, you run the risk of spending months waiting to see that what was designed doesn't work. In this case, it was having SPICE show you in the time domain that the circuit was not stable. This is where having a good mentor network is important. People who will help you identify all the questions that need to be asked on SPICE, help make sure the models capture all the important aspects so the simulation results are valid, etc. etc. Good luck Luis. I'm going to step aside from this thread now.

Hi, how can I to do this ?