<!channel>: Announcing (finally!) the availability of the caravan analog and mixed-signal harness chip and the caravel_user_project_analog repository, where you can download the wrapper for analog user projects. The user project system works in the same way as the standard user project wrapper, with essentially the same instructions for submission and running pre-check through efabless. See the repository for more information: Caravel analog user project repository . And flag me down in this channel if you have any questions, concerns, or needs. Thanks for your patience!

I have been focused on design right now and have not reviewed much of the submission stuff, but I know they want a test simulation for submitted digital designs. What sort of verification is required for analog designs?

@Weston Braun How are you going to test the chip when you get it in your hands?

I was going to design my own PCB for it. Most of the sub-modules can be isolated and externally verified by disabling other modules (which can be done with muxes connected to I/O)

Hmm, in that case, the PCB design would be nice, and perhaps a test-plan in text form?

We are asking for a verilog top level. That means creating some sort of module representing the analog. The best thing to do is to create a lightweight behavioral model that can be used with a verilog testbench to make sure that the management SoC comes up and configures the GPIO properly so that you can access any GPIO pins you might be using. In the worst case, just create an empty "black box" entry for it. It is used on our side for ensuring the connectivity between the user project wrapper and the rest of the caravel/caravan chip. We want to eventually be able to take a top level SPICE netlist for this purpose, but right now we have only the verification by verilog.

@Weston Braun What would be your plan for testing the chips in mass-production?