I am seeing "VSUBS" appear in some of my extracted...
# analog-design
I am seeing "VSUBS" appear in some of my extracted files, but not really connected in any coherent way. Spice does not have global variables, right? I am seeing it getting passed in as a signal to one subcircuit and not being used, and seeing it used in another subcircuit without being passed in
SPICE does have one global net "0" which is the substrate; also you can declare any net global with ".global <name>". "VSUBS" is the substrate node. It will appear all over the place but it should never be considered global. But there are still issues with substrate extraction that I have not had time to work through; the fixes I'm working on should get rid of those instances where the substrate manages to end up in a subcircuit without being declared as a pin (and possibly fixes the vice versa case, too, although that's less of an issue). A ".global VSUBS" is probably the best way to deal with it for now.
The issue here is deeper than that though. This is a fet in an isolated nwell. So there should be no common substrate connection
When I flatten the design it seems to match what I expect though. So it relates to the deep nwell layer being in a separate module?
I am also seeing the other case in this unflattened design, the pmos takes the subcircuit pin but does not use it