<@U016EM8L91B> When running LVS, I occasionally ge...
# analog-design
@User When running LVS, I occasionally get pin mismatches labeled in the comp.out file. However, the results say everything matches correctly, including the cell pin lists. Is this something I should be worried about/need to double check? I've attached an example in the comments.
There was an error in netgen regarding pin mismatches (specifically, netgen ignoring them) that I fixed yesterday. It was not quite the same situation, so I'm not sure if it applies or not. The bottom line is, though, that just a pin name difference at the top level is not expressly an error, since the schematic and layout might simply disagree on nomenclature. If they are connected differently at the next level of hierarchy, then it will definitely be flagged as an error. Netgen treats the pins as strings only; it does not have the smarts to understand that the pin matches are all inside what looks like an array with the number scrambled.