I very much have no idea what I'm doing in terms of layout... In university they seemed to think it's just a boring mechanical thing you'd just pick up on the job if needed, except I went on to write FOSS EDA software instead of get an IC design job... Trying to make a basic current mirror with 3 ports. So Tim suggested I use -/+40 via coverage so I can route across, which is great for the sources, but the drains need individual outputs and when I route out that way it clashes with the gate contacts. So I guess I have to only have gate contacts on one side, but then the current input drain needs to be routed all the way across to the gate, which seems unfortunate. He also suggested I add dummy devices, so I have 7 fingers of which I'm only using 3, but maybe I actually only want 5 with the 3 middle ones being used for the current mirror? What do I do with the rest? Just leave them hanging, or ground them for noise and such?

re: Dummies, you don't want to leave them floating. If these are NMOS you could connect them to ground, if they're PMOS VDD. In general, you'd want minimal impact from these so, minimal capacitive load and minimal current draw.

In general, I make my current mirrors this way. I try to keep vertical wires or in odd metal layers or even metal layers. In this case, locali for horizontal and metal1 for vertical. I avoid to connect even dummy gates to the power supplies, as it can result in DRC antenna errors later. In this case, I short circuit both drain and source terminals to the ground and connect the dummy gate to the the mirror gate input. This way, since VDS = 0 V, there is no current.

^ I agree with Luis. I should have been more clear, connect the gate to whatever the remaining gates are connected to for uniformity. Just ensure VDS = 0, don't leave any terminal floating.

Literally HOW are you routing between the gate contacts? Both metal1 and locali give DRC errors.

Can't you increase the internal diffusion width?

My level of understanding of all these layers is basically a texbook mosfet image. AFAICT you're referring to the drain/source N+/P+ area... I don't see an option for it in the magic pcell window. Only option is to join them so you basically get disconnected mosfets instead of fingers. And set the percentage of diffusion contact coverage.

It's probably not intended for the support long channel...

I think I can work around it with unmerged diffusion contacts or smaller via contacts.

Won’t your matching suffer if you un-merge the diffusions?

I mean, maybe a bit because they ar further apart but it's still a closely packed array of devices with dummies on each side, so I'm hoping it'll be fine.

My solution would be to not select the via option for the gate contacts, and then contact the gates across in local interconnect. Then you can pass the source and drain connections over them in metal1.

Hm that seems like a nice option. IIRC you said to not use local interconnect because it's high impedence, but I guess for low speed gate connections it's fine.

I'm making all the vias and contacts manually, so they fit ok. If you use large vias from metal1 to locali, there won't be enough space to route parallel metal1 wiring. Also, you can use multifingered transistors, so it has lots of space for routing. Locali-poly contacts have high-impedance, but if you use lots of them in parallel, it is no problem at all.

Yea it seems nobody is actually using the PCells and just drawing all the transistors by hand. I feel like I don't have the knowledge about the layers, DRC rules, and magic commands to do that in any sort of reliable way. Maybe this is why Weston suggested using a lot of TCL to draw all the things at repeatable sizes and distances.

I'm not using the TCL script just because I don't know how to use them. If I knew, I could maybe make a script to make the current mirror above automatically. It's not that hard.

How do you make all the transistors the same size and distance that matches the schematic?

Schematic? What is it? : ] I make the layout, extract the netlist and it matches perfectly with the netlist it generates. The best way for LVS.

@Pepijn de Vos: In magic there is a menu item File->Import SPICE that is not good enough to do your entire layout for you, but it will generate all devices to match the schematic. You will then need to modify the resulting parameterized cell parameters since the schematic does not capture all of the nuances of the parameterized cell. I can always extend the parameterized cell with additional features, if there are common use cases that warrant it.

Not sure how helpful that is going to be when your schematic "device" does not correspond to the layout "device" because you group them for matching. And my problem is not instantiating PCells, but rather routing them. If I use the via option it goes up to metal1 and without it there is not enough space inside the guardring to connect it to locali manually.

It is always possible to edit a parameterized cell. You can just go in and stretch all the contacts to the size you want. The only caveat is that once you do that, you can't use the parameterization pop-up window and change parameters or else it will redraw the cell and overwrite your edits.

@Pepijn de Vos you can also route it out with reduced via coverage if you use longer devices

Why?

Short channel effects. You get a higher output resistance with larger length

Sure but it's also slower. Actually for the current mirror it would probably be good. For getting the most speed out of some other parts, probably not. I would be the first to admit that this opamp design wasn't complete though haha, I just wanted to get something on this shuttle but really underestimated layout. Maybe next shuttle I'll have an actual okay design.

Do you need the bw? You can get multi hundred MHz bw without minimum length transistors

Yea I was aiming for 500MHz which the current design barely makes. It's probably far from optimal though.