<@U016EM8L91B> I just found a serious error in the...
# analog-designw
Weston Braun
06/18/2021, 5:21 AM@User I just found a serious error in the netgen setup (I think its possibly an error in the netgen setup file and not netgen?): the inputs and outputs of the sky130_fd_sc_hvl__inv_8 gate can be flipped between two netlists and it still passes lvs. Please see the two attached netlists as an example. Look at net rampgen_io
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Tim Edwards
06/18/2021, 3:44 PMUnder review and totally mystifying.
Tim Edwards
06/18/2021, 4:29 PMThere is something truly wacky about this example. I reduced it to just the layout vs. layout with the two nodes swapped, and removed everything from the file but the oscillator subcircuit, and didn't pass any setup file. It still passes. If I then remove all the trasnsistors from both subcircuits, it suddenly notices that the pins are swapped and fails.
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Weston Braun
06/18/2021, 4:46 PMI found it only because it was passing lvs without the cap on the vramp node, but anything added to that node at all caused lvs to fail
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Tim Edwards
06/18/2021, 9:52 PMIt gets weirder and weirder. I have reduced the problem to a 6-line circuit that looks normal in every way, but I can swap the first and last pin connections on the last device and netgen doesn't notice. It is not clear to me at all what's going on, but my simplified case is so simple that I should be able to step through the matching and watch what netgen is doing.
Tim Edwards
06/19/2021, 2:11 AMThis contains two files test1g.spice and test2g.spice, technology-non-specific, that is your example pared down to pretty much a bare minimum. The first and last pins of the last device are swapped, and netgen doesn't notice and says that the netlists match.
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Weston Braun
06/19/2021, 2:55 AMGood regression test for netgen in the future! 😅
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Tim Edwards
06/19/2021, 5:27 PMThis is less of a regression test and more of an existential crisis test.
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Weston Braun
06/19/2021, 7:57 PMFound the root cause yet?
Weston Braun
06/19/2021, 7:58 PMIdeally I would run LVS on my design before actual tapeout with this bug fixed
Weston Braun
06/19/2021, 7:59 PMSorry I just found this error now, was not the best time to find it 😶
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Tim Edwards
06/19/2021, 8:05 PMYes, but these things get exercised a lot more in a run-up to a tapeout. I had to remind myself yesterday that it's to be expected, and that I shouldn't be going bonkers because everything seems to be breaking all at once. A lot of people working in parallel can uncover a lot of corner cases really quickly.
I'm pretty well convinced that this particular error has nothing to do with any changes I've made recently. Netgen seems to continue to work in the vast majority of cases. It does, however, tend to indicate that pathological cases that are missed are not "diminishingly small" as they are supposed to be. You wouldn't randomly happen upon a case with infinitesimal probability.
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Weston Braun
06/19/2021, 8:20 PMI do seem to have a knack for finding weird edge cases 😅