@User I just found a serious error in the netgen setup (I think its possibly an error in the netgen setup file and not netgen?): the inputs and outputs of the sky130_fd_sc_hvl__inv_8 gate can be flipped between two netlists and it still passes lvs. Please see the two attached netlists as an example. Look at net rampgen_io

Under review and totally mystifying.

I found it only because it was passing lvs without the cap on the vramp node, but anything added to that node at all caused lvs to fail

It gets weirder and weirder. I have reduced the problem to a 6-line circuit that looks normal in every way, but I can swap the first and last pin connections on the last device and netgen doesn't notice. It is not clear to me at all what's going on, but my simplified case is so simple that I should be able to step through the matching and watch what netgen is doing.

Good regression test for netgen in the future! 😅

This is less of a regression test and more of an existential crisis test.

Found the root cause yet?

Yes, but these things get exercised a lot more in a run-up to a tapeout. I had to remind myself yesterday that it's to be expected, and that I shouldn't be going bonkers because everything seems to be breaking all at once. A lot of people working in parallel can uncover a lot of corner cases really quickly. I'm pretty well convinced that this particular error has nothing to do with any changes I've made recently. Netgen seems to continue to work in the vast majority of cases. It does, however, tend to indicate that pathological cases that are missed are not "diminishingly small" as they are supposed to be. You wouldn't randomly happen upon a case with infinitesimal probability.

I do seem to have a knack for finding weird edge cases 😅