Hello I am testing LVS over the user analog project wrapper

Question

Hello I am testing LVS over the user analog project wrapper in a minimal design with just 1 opamp I have excluded other cells in order to isolate the error Initially netgen says for both nfet and pfet ```Warning Equate pins cell sky130 fd pr nfet 01v8 has no definition treated as a black box ``` and at the end of the comparison file it states ```Device classes user analog project wrapper spice and user analog project wrapper layout spice are equivalent Verify cell user analog project wrapper layout spice has no elements and or nodes Not checked ``` Does someone experienced this behaviour I understand that netgen is not reading the transistors in the extracted file then no comparison is made

yrrapt · Answer

Are you using the sky130 netgen configuration script when you run netgen

yrrapt · Answer

Also I don t think your vdd or iref pins are correctly connected to the user analog project wrapper pins

Fredy Solis · Answer

yes I am using the script provided by open pdks

Fredy Solis · Answer

that s correct the iref pin have been left unconnected in this version in both sch and layout but the vdd should be ok I ll check that thank you

Fredy Solis · Answer

I have solved this issue have been extracting the top level layout using ```extract all ext2spice lvs ext2spice o cell ext spice``` this created a subcircuit instance of the top layout The netlist matches uniquely after commenting out the lines containing the ports and the subcirtuit declaration i e including only the instances of our cells

yrrapt · Answer

Good to hear you solved it

Fredy Solis · Answer

Thank you < yrrapt> raised hands Now dealing with the GDS file