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subckt

inv_pex_2

Screenshot from 2021-10-17 18-10-57.png

we are running post layout simulation for a simple inverter included in the following files:
but we get zero output as shown below
Any help <@U016EM8L91B> <@U01819B63HP> Thanks in advance

Your subcircuit pins are

```.subckt TOP INPUT OUTPUT GND VDD```
while your testbench instance is

```Xs INPUT OUTPUT VDD 0 TOP```


This happens because when you extracted the circuit from the layout, the GND pin was labeled first. Spice is a really bad language for pin order...