we are running post layout simulation for a simple inverter open-source-silicon #analog-design

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Title

m

Mustafa Ahmad

10/17/2021, 4:11 PM

we are running post layout simulation for a simple inverter included in the following files: but we get zero output as shown below Any help @User @User Thanks in advance

subckt inv_pex_2

l

Luis Henrique Rodovalho

10/17/2021, 6:32 PM

Your subcircuit pins are

Copy code

.subckt TOP INPUT OUTPUT GND VDD

while your testbench instance is

Copy code

Xs INPUT OUTPUT VDD 0 TOP

This happens because when you extracted the circuit from the layout, the GND pin was labeled first. Spice is a really bad language for pin order...

m

Mustafa Ahmad

10/17/2021, 6:39 PM

OH i am sorry okay thanks