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#analog-design
Title
# analog-design
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Nikhil M

11/27/2021, 5:46 AM
Hi Guys, I'm trying to make a power nmos I have used the multiplicity parameter in my spice file but in my layout I have made it using several nmos in parallel is there anyway I can get the LVS check not to fail because in the netgen LVS it has defined each transistor as a different net.
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Matthew Guthaus

11/27/2021, 3:47 PM
Are you using the open_pdks setup.tcl? Providing a test case might help us debug. There is a "parallel" property in netgen..
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Stefan Schippers

11/28/2021, 2:22 AM
@User Are the transistors truly in parallel? that means all transistor terminals are connected together (gate to gate, source to source and so on). How can netgen assign a different net to each?
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Eric Smith

11/30/2021, 6:45 PM
I think you mean like in section 3.2.1 of the ngspice manual right? http://ngspice.sourceforge.net/docs/ngspice-html-manual/manual.xhtml#tab_multiplier
That’s not going to pass LVS because ngspice will autogenerate names for the parallel devices that don’t exist in the netlist, so the netlist compare can never pass.
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Nikhil M

12/13/2021, 4:47 PM
@User yes that’s right. Doesn’t pass on netgen. Sorry for the late response i was out sick for 2 weeks
@User yes they are completely in parallel. I used the setup.tcl mentioned by @User didn’t work. Not sure if we need an enhancement on Netgen to deal with this when M factors are present
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Matthew Guthaus

12/13/2021, 5:58 PM
@User You need to provide a test case.
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Nikhil M

12/13/2021, 6:03 PM
@User sure ill set up an LVS and get back.