I'm trying to make a power nmos I have used the multiplicity parameter in my spice file but in my layout I have made it using several nmos in parallel is there anyway I can get the LVS check not to fail because in the netgen LVS it has defined each transistor as a different net.
11/27/2021, 3:47 PM
Are you using the open_pdks setup.tcl? Providing a test case might help us debug. There is a "parallel" property in netgen..
11/28/2021, 2:22 AM
@User Are the transistors truly in parallel? that means all transistor terminals are connected together (gate to gate, source to source and so on). How can netgen assign a different net to each?