Is there a way to convert a Verilog netlist to SPICE netlist to perform a mixed-signal simulation on a gate level with analog circuitry?

@Domagoj Tomić If you are going to do a GLS then why do you need the SPICE netlist?! If you are doing SPICE sim then why do you need GLS?! You can do a full-chip SPICE sim by doing the PD of the mixed-signal chip and then simulate the final SPICE netlist. Or just try for a less accurate simulation by doing the PD for the Verilog and combine the final SPICE netlist with the analog SPICE netlist.

@User I'm trying to do a mixed-signal simulation so the first idea was to create a behavioral SPICE model from the Verilog netlist and then incorporate it into my analog design SPICE netlist. It is important that the gate delays are simulated correctly alongside the analog simulation. The other alternative is to do transistor level simulation, there I also need to map the Verilog netlist into SPICE netlist where digital cell models from the sky130 lib are placed in. Since the Verilog netlist is practically already describing that the conversion to SPICE netlist shouldn't be hard, however I can't find any documentation on how to do it. I know I can extract the netlist from layout, but I need to do this simulations before P&R.

@Domagoj Tomić https://electronics.stackexchange.com/questions/117244/verilog-to-spice-using-v2s-specificing-the-port-order-in-the-command-v2s

Thank you,

yosys -p 'write_spice test.sp' test.v

was the line that did it, I was not aware that yosys had that capability.

@Domagoj Tomić: A better solution is to use

spi2xspice.py

from

qflow

. The xspice representation of a digital standard cell circuit runs a bit slower than it would in an equivalent gate level verilog simulation, but it runs many orders of magnitude faster than simulating the digital circuit at the transistor level.