Domagoj Tomić12/12/2021, 8:48 PM
manili12/12/2021, 9:44 PM
Domagoj Tomić12/12/2021, 10:43 PM
manili12/13/2021, 12:14 AM
Domagoj Tomić12/13/2021, 12:32 AM
was the line that did it, I was not aware that yosys had that capability.
yosys -p 'write_spice test.sp' test.v
Tim Edwards12/13/2021, 2:46 PM
. The xspice representation of a digital standard cell circuit runs a bit slower than it would in an equivalent gate level verilog simulation, but it runs many orders of magnitude faster than simulating the digital circuit at the transistor level.