Domagoj Tomić
12/12/2021, 8:48 PMmanili
12/12/2021, 9:44 PMDomagoj Tomić
12/12/2021, 10:43 PMmanili
12/13/2021, 12:14 AMDomagoj Tomić
12/13/2021, 12:32 AMyosys -p 'write_spice test.sp' test.v
was the line that did it, I was not aware that yosys had that capability.Tim Edwards
12/13/2021, 2:46 PMspi2xspice.py
from qflow
. The xspice representation of a digital standard cell circuit runs a bit slower than it would in an equivalent gate level verilog simulation, but it runs many orders of magnitude faster than simulating the digital circuit at the transistor level.