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#analog-design
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# analog-design
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Nikhil M

12/13/2021, 5:53 PM
Hi Guys, Can someone point me in the direction of what the maximum transistor sizes with the sky130 process is. I did some testing and looks like the spice models work only upto w of a certain size beyond that they fail saying no model found
looks like for the 1.8v NFET 100 micron is as large as it can go
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Luis Henrique Rodovalho

12/13/2021, 8:23 PM
This file has all the MOSFET dimensions that really work. Any other sizes results in interpolated models. The maximum size is 7/8 um. https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]d6f59b57627436/cells/nfet_01v8/sky130_fd_pr__nfet_01v8.bins.csv
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If you really need larger transistors, you can always use transistor arrays. This way you can achieve any transistor aspect ratio using any single transistor as building block. It works and follows the strict transistor models from the foundry. https://lci.ufsc.br/pdf/_00309905.pdf
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Nikhil M

12/14/2021, 1:29 AM
Thank you @User
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Eric Smith

12/16/2021, 8:04 PM
When you make transistor arrays you have to think a lot about the layout. For example waffle structures give the most W per area but they also have a lot of corners and other disadvantages. If you’re doing a load switch, and managing the transient, then this can be no problem. If you’re doing a DC/DC, like a charge pump or something, that can be bad. So there are other possible options for those. Google bent-gate or stripe FET layout. Chapter 12 in the Art of Analog Layout by Alan Hastings (used copied can be had cheap) has a good digression on it. Be prepared to fight LVS… :)