When you make transistor arrays you have to think a lot about the layout. For example waffle structures give the most W per area but they also have a lot of corners and other disadvantages. If you’re doing a load switch, and managing the transient, then this can be no problem. If you’re doing a DC/DC, like a charge pump or something, that can be bad. So there are other possible options for those. Google bent-gate or stripe FET layout. Chapter 12 in the Art of Analog Layout by Alan Hastings (used copied can be had cheap) has a good digression on it.
Be prepared to fight LVS… :)