Hello All, I'm struggling a bit with the analog la...
# analog-design
Hello All, I'm struggling a bit with the analog layout using magic, I found two approaches: 1. Draw poligons from scratch as in BMINCH's youtube tutorials (e.g.


) a. The main pros are that you get to understand pretty well the layer configuration and make sense of your layout for possible optimization b. The cons are that it may get hard to manage for big designs 2. Import the devices from the top top menu, e.g. "Device 1" where you have the basic nmos and pmos (e.g. as in this video around minute 17.44:


). a. Pros: fast and easy to generate devices, mostly if you have several fingers and want to include guard ring b. Cons: I managed to generate nmos and pmos for an inverter, but in the case of multiple fingers, it generates also the metals and the vias and I'm finding it difficult to connect or edit the generated cells Any opninions or advice on which approach is more convenient in the context of SKY130? I guess it's really personal but I'd like to read what people here are doing. Also, for the second case, do you know maybe how can I edit the generated cells if I want to remove or add some poligons to what is generated by default?
You really want to use the device generators, as some parameters, such as the channel to contact spacing, are important for the models to match
There are a lot of paramters you can edit when you call the device generator to alter / remove some of the contact layers (such as the gate M1 contacts)
You can also call the device generator functions directly via TCL. I did the initial placement for my designs using TCL scripts, which makes it easy to align everything. I then did most of the routing between transistors by hand. Here is an example script: https://github.com/westonb/open-pmic/blob/master/layout/folded_cascode_n_in/folded_cascode_n_in.tcl
Usually, I make the layout of an analog cell of a single transistor, or any other simple analog structure, as a current mirror or differential pair. After that, I make another cell using these basic blocks, so I never really have to make the layout of a transistor again, and I just need to connect those basic analog cells with metal wires.
Magic VLSI is perfect for designing standard cell logic gates, or viewing and checking the layout of a full digital block. It can work for analog projects, but it lacks a lot of important tools, as highlighting short circuits or showing incomplete nets. It can work well with high-level custom designs, after the most basic blocks are done from scratch. Other than that, LVS error finding and correction is nightmarish without a proper GUI.
@Luis Henrique Rodovalho: Magic can highlight short circuits, show incomplete nets, and has a method for tracing nets that is easier to use than any other tool I know of.
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@Jorge Marin: Try to work with the parameterized cells as specified; you can remove the guard ring and various contacts and can make it basically as simple or complex as you want. Otherwise, there are two options: (1) Create a parameterized cell, then select everything inside it, use the "copy" command to copy all of that to the top level layout, which effectively flattens the cell contents, then delete the cell. (2) You can edit any parameterized cell. Just be aware that if you ever select that cell, pull up the parameter pop-up window, and hit "Apply", all your edits will be undone.
@Tim Edwards Then there is a problem between the screen and the chair... :] I must study the tool a bit more. My analog flow is far from completion. Anyway, in my opinion, magic biggest strength is that it is open source and it is TCL, so we could make easily scripts to place and route analog blocks. We are just not there yet.
The traditional approach is to blame it on lousy documentation. : )
By the way, where is the convert to png command for the plot pnm?
hello @User, @User and @User, thanks a lot for your valuable feedback. I am following Tim's advice to lay out a CMOS inverter with multiple fingers: after doing File --> Import SPICE, I copy the cells and erase the original ones. I edit and connect the copies, and then I extract the SPICE netlist to compare with the schematic netlist. Netgen shows that the netlists don't match due to a capacitor device generated between supply and ground in the layout extracted schematic. After commenting the capacitor in the netlist, Netgen reports matching between layout and schematic. How to deal with this? I don't understand where this 3.64fF capacitor in the layout-generated schematic comes from and how to make it match the schematic. any help is appreciated!
@Jorge Marin: These are parasitic capacitances. You want them for simulation (makes the simulation more realistic), but you don't want them for LVS. When you extract the circuit in magic, use
ext2spice lvs
followed by
, and you will get a netlist that is appropriate for LVS, and doesn't contain parasitics.
Thanks for the explanation, Tim. Question: why does ir only extract the supply-gnd capacitance and not the other nodes? Are there any parameters to set this?
@Jorge Marin: Probably the other capacitances are below the threshold. Use
ext2spice cthresh 0
if you want to see every single parasitic cap.
@Vicente Osorio