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b

Brandon Ong

01/11/2022, 7:29 PM
Has anyone added a macro that was drawn by hand to the caravel harness? If so could you show how you configured the caravel_user_project
a

Arman Avetisyan

01/11/2022, 8:22 PM
I just opened the caravel_user_project and modified it as I wished. Probably the empty wrapper is better starting point though
The GDS is called user_project_wrapper.gds. I used KLayout and Magic. The workspace can be downloaded from github. Its called caravel_user_project
b

Brandon Ong

01/11/2022, 8:26 PM
Thanks but I was hoping to insert my custom macro into the project and have it generate the final gds instead of editing it myself
a

Arman Avetisyan

01/11/2022, 8:33 PM
Just copy and paste the macro into the wrapper. But proper way I would assume is using OpenLane to generate user_project_wrapper.
b

Brandon Ong

01/11/2022, 8:34 PM
Were you able to get it through check for the shuttle?
a

Arman Avetisyan

01/11/2022, 8:35 PM
Not yet, but if you tell me what the issue is exactly then I could try to help with the issue itself.
b

Brandon Ong

01/11/2022, 8:36 PM
I'm having trouble connecting vdd and gnd to the power pins. I thought it would do it automatically, but it's not working
So, for example, most of my pins are routed correctly, but vccd1 and vssd1 are left disconnected
a

Arman Avetisyan

01/11/2022, 8:38 PM
So you ran OpenLane with your custom Macro based on Caravel User Project but generated wrapper didnt have connected VDD/VSS is this correct?
b

Brandon Ong

01/11/2022, 8:38 PM
Exactly
a

Arman Avetisyan

01/11/2022, 8:39 PM
Does verilog (top level netlist) contain the connection of VDD/VSS to VCCD1/VSSD1?
m

Matt Venn

01/11/2022, 8:39 PM
I think @User knows how to do this
b

Brandon Ong

01/11/2022, 8:42 PM
@User I named the pins vccd1 and vssd1 because it was causing errors. So that may be the problem
a

Arman Avetisyan

01/11/2022, 8:46 PM
what errors was pin name vdd/vss causing that you had to rename it?
b

Brandon Ong

01/11/2022, 8:47 PM
If I remember correctly, it was saying I didn't have vccd1 connections. I'll try including vdd&gnd and connecting them in verilog
I'm getting this warning, and then it errors out
Warning: No pins in the LEF view of u_flash_array_8x8  marked for use as power
a

Arman Avetisyan

01/12/2022, 12:58 PM
Did you use Makeport of Magic VLSI and set the class to power before generating the LEF?
b

Brandon Ong

01/12/2022, 2:59 PM
@User I'm not sure what you mean by makeport
a

Arman Avetisyan

01/12/2022, 4:33 PM
https://github.com/praharshapm/vsdmixedsignalflow Section: Other important fields of LEF file
p

Philipp Gühring

01/14/2022, 7:20 PM