Has anyone added a macro that was drawn by hand to the carav

Question

Has anyone added a macro that was drawn by hand to the caravel harness If so could you show how you configured the caravel user project

Arman Avetisyan · Answer

I just opened the caravel user project and modified it as I wished Probably the empty wrapper is better starting point though

Arman Avetisyan · Answer

The GDS is called user project wrapper gds I used KLayout and Magic The workspace can be downloaded from github Its called caravel user project

Brandon Ong · Answer

Thanks but I was hoping to insert my custom macro into the project and have it generate the final gds instead of editing it myself

Arman Avetisyan · Answer

Just copy and paste the macro into the wrapper But proper way I would assume is using OpenLane to generate user project wrapper

Brandon Ong · Answer

Were you able to get it through check for the shuttle

Arman Avetisyan · Answer

Not yet but if you tell me what the issue is exactly then I could try to help with the issue itself

Brandon Ong · Answer

I m having trouble connecting vdd and gnd to the power pins I thought it would do it automatically but it s not working

Brandon Ong · Answer

So for example most of my pins are routed correctly but vccd1 and vssd1 are left disconnected

Arman Avetisyan · Answer

So you ran OpenLane with your custom Macro based on Caravel User Project but generated wrapper didnt have connected VDD VSS is this correct

Brandon Ong · Answer

Exactly

Arman Avetisyan · Answer

Does verilog top level netlist contain the connection of VDD VSS to VCCD1 VSSD1

Matt Venn · Answer

I think < U02NTJQUQ8K> knows how to do this

Brandon Ong · Answer

< U01UTPXQ2NQ> I named the pins vccd1 and vssd1 because it was causing errors So that may be the problem

Arman Avetisyan · Answer

what errors was pin name vdd vss causing that you had to rename it

Brandon Ong · Answer

If I remember correctly it was saying I didn t have vccd1 connections I ll try including vdd amp gnd and connecting them in verilog

Brandon Ong · Answer

I m getting this warning and then it errors out `Warning No pins in the LEF view of u flash array 8x8 marked for use as power`

Arman Avetisyan · Answer

Did you use Makeport of Magic VLSI and set the class to power before generating the LEF

Brandon Ong · Answer

< U01UTPXQ2NQ> I m not sure what you mean by makeport

Arman Avetisyan · Answer

<https github com praharshapm vsdmixedsignalflow> Section Other important fields of LEF file

Philipp Gühring · Answer

<https github com thesourcerer8 caravel stdcelllib stdcells project|https github com thesourcerer8 caravel stdcelllib stdcells project> you can see there how I did it