Can someone point me to a source of truth on nmos and pmos geometry limits on W and L? Specifically for sky130_fd_pr__nfet_01v8 and sky130_fd_pr__pfet_01v8

The "truth" is in the original SkyWater Calibre decks or somesuch, and the ranges that are specified by DRC rules on device type gate widths would have to be pulled out of those files. The device models have ranges for wmin/wmax and lmin/lmax which can also be used for that, but there are properties that are not continuous across those boundaries, so it's clear that the devices were characterized over a smaller range than is specified by wmin/wmax and lmin/lmax.