@User I believe in simulation you can set a latch in metastable state forever if you are lucky enough. A similar case happens when simulating a chain of -say- 7 inverters connected in a ring oscillator. If the inverters are identical simulation could converge to the metastable solution where all voltages are ~Vcc/2. In real life the ring oscillator will soon start oscillating, since thermal noise, supply noise, coupling and other effects will push the circuit state away from this metastable state. However in a simple transient simulations all these effects are not considered. In some cases you just need to deliberately put a small unbalance in the ring oscillator fo force it oscillating, or probe some current into one of the stages to move it away from metastability. I said "lucky enough" since numerical errors in the calculation of the circuit voltages and currents could play the same effect as thermal noise in the real circuit, and move it away from the unstable equilibrium point. But how fast this happens has nothing to do with real life circuits. It depends on the integration method, the time step and residual error tolerance.

very useful, thanks Stefan

During power on of a chip the supply voltage is gradually going up when all the decoupling and parasitic capacitances are charged. After this ramp-up the flipflop will be either in 0 or 1 state determined by the mismatch between the transistors in the latches and noise.

np, appreciate the effort!

@User no problem, feel free to use anything useful :-)

😊

I will look at the video, I have lot to learn from the digital flows

, I'm just about to make a round of improvements. Will send you a link to a preview

Your videos are in general very clear, also due to the clear English speaking, good for non US/UK/AU natives.