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I think I have one of the first opamps taped out o...
# analog-design
w
I think I have one of the first opamps taped out on the sky130 PDK and amcharacterizing it now. I actually lost my sim data so im going to need to setup the toolchain again and run some sims to see what the expected specs were supposed to be. But I have my first bode plot of my simple P input cascode opamp! (error amplifier for my PMIC). low frequency gain is ~43dB. Offset voltage on the bench is 2.4mV. https://github.com/westonb/Open-PMIC-tapeout/blob/main/xschem/folded_cascode_p_in.sch
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Typically designs use arrays of FET fingers for better matching / ease of layout
Look up common centroid layout, it allows for better matching
also, you can reduce capacitance. for example, if you have two 5x1 FETs instead of one 10x1 you can have the drain region be shared, so you only have less capacitance to the substrate.
a
@manili No
Adding fingers mainly reduces the capacitance and it's generally better for matching and common - centroid design in general.
But it comes with extra routing on the other hand which adds more capacitance as well.
@manili In many companies, it's a requirement for layouters to do the design in Common-Centroid. Even there are DRC/Advanced DRC checks for that implemented.
@manili If you are asking from the modeling side, the CGD CGS CDG should be different.
It should be lower.
If they are not different, then I would say the model has an issue most probably either from the simulator or the model card.
I hope this helps.
m
@Weston Braun @Amro Tork Thanks a lot for sharing these invaluable info and docs. I’m pretty much new to the custom/analog layout design and currently trying to learn by doing. So I’ll read your info in advance and BRB with more questions. 😀 Thanks again.
a
@Weston Braun Whats the function of M17 and M14, for ensuring a diode voltage across GD ?
w
They are diode connected. it helps with improving the slew rate / large signal response
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This design is based off the design of the folded cascode opamp in "Analog Integrated Circuit Design, 2nd edition", which details it a bit more. Chapter 6.4, page 269 in my copy
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if you look online you should be able to find a PDF copy 🙃
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