Hi, I'd like to use the analog version of the cara...
# analog-design
Hi, I'd like to use the analog version of the caravel and need some ESD protection. The 1.8V ESD FET described here https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html?highlight=ESD#nmos-esd-fet seemed to be a good choice. Spice simulations show this transistor is nice. It seems I can go up to 1 GHz and beyond with it. However, I cannot find any layout information on it. Has anyone used it? How do you implement ESD protection?
Well, good question. I am also interested in the answer. You can take a look at esd cell in gpio. IDK how it works, but has a resistor
It uses different esd nfet.
Yea that's really a pitty. Seems the data is already missing in the PDK. This folder only contains spice models, but no layout: https://github.com/google/skywater-pdk-libs-sky130_fd_pr/tree/f62031a1be9aefe902d6d54cddd6f59b57627436/cells/esd_nfet_01v8. This FET would be great to make a GGNFET ESD protection.
@User: There are layouts for the ESD nFET in the newer s130 PDK from SkyWater (the proprietary one). I will see if we are allowed to open source the layout, or at least post documentation of the actual numbers for the conservative rules cited in the existing documentation.
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@User Thank you!
@User Thanks !
@User Any update? Submission deadline is approaching!
Sorry for not getting back to you on this. I was on travel for a bit. I'm discussing it with Tim Ansell now. It appears that there is no issue with open-sourcing the spec or the layout. I just need to get it converted from Open Access.
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@User: I got the SkyWater parametric cells for the "ESD" FETs converted from the s130 PDK and. . . they look just like regular FETs. I can't see anything special about the layout at all which would make it an "ESD" FET. In fact, as the parameterized device is drawn, it violates SkyWater design rules (there is only one tap and it is too far away from the other end of the transistor to satisfy latchup requirements). It does have a minimum length of 10um (which is odd, and is what causes the tap distance error). There are clearly no "conservative rules" as was hinted at in the documentation. If I ignore the documentation altogether, usually the rule for ESD protection is to use an extended drain device, since that puts a diode and resistor right at the device. For ESD protection on an input gate, I'd just suggest a resistor and diode near the gate.
Thank you! That's strange. I was expecting something like in image c. The main difference being a larger nwell at the drain and a deep nwell connection under the drain. But I'll use diodes for protection then.
@User: What you show in the diagram is an extended-drain device. That's different from the
that you referenced in the documentation. Look instead here: https://skywater-pdk.readthedocs.io/en/main/rules/device-details.html?highlight=ESD#v-16v-nmos-fet . As you can see from the diagram, that structure has the n-well under the gate and stretching to the drain. It is a standard thick-oxide device (Vgs <= 5.5V) but can tolerate up to 16V across S-D.
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