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#analog-design
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# analog-design
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Leonardo Gomes

04/17/2022, 12:31 AM
My first design is coming up rather nicely :) An LC tank for a 60GHz VCO. I did PLS on the tank (asitic for the coil, magic PEX for the varactors) and it's starting to take shape! Still to do: cross-coupled pair, coil guard ring, output buffers.
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Ryan Wans

04/17/2022, 2:11 PM
One of the default PCells in the Klayout deck is a guard ring / shield for inductors
Either “rectangular_shielding” or “triangular_shielding”
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Leonardo Gomes

04/17/2022, 2:17 PM
Thanks for the link :) But I meant something else. Shielding for inductors at these frequencies create more losses than just the Si eddy currents alone, I meant a P+ guard ring around the inductor to limit cross-talk. Actually, from my own experience, blocking the P- doping and the silicide inside/around the inductor is more effective than the shielding
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Amro Tork

04/17/2022, 3:22 PM
@User In the PCells mentioned above, you could remove the Filler Metal.
Unfortunately we didn't add a gaurd ring around the inductor.
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ArunAshok

04/26/2022, 5:13 PM
Great work! Was the inductor itself part of the pcell or was it synthesized
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Leonardo Gomes

04/26/2022, 5:28 PM
Thanks! It's part of @User's Pcell generator :)
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ArunAshok

04/26/2022, 7:03 PM
@User @User Could you please provide the link for the pcell gen
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Leonardo Gomes

04/26/2022, 11:06 PM
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Amro Tork

05/09/2022, 8:17 AM
@User