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ok, next step - try to create a new design
# openlane
m
ok, next step - try to create a new design
I created the design with this: ./flow.tcl -design inverter -init_design_config
the design is in src/inverter.v
image.png
and then ./flow.tcl -design inverter fails with this
image.png
a
This is interesting; thanks for raising this. The thing is that the design is very tiny (2 cells). So with a high core utilization (see the FP_CORE_UTIL setting here), you get a very tiny layout, which is smaller than the default pitch of the power grid. You can control both the utilization and the PDN stripe pitches using some configurations variables. I suggest setting the utilization to a low value to get a larger layout. For example, try appending the following into your 
designs/inverter/config.tcl
:
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set ::env(FP_CORE_UTIL) 10; # 10 % utilization
set ::env(FP_PDN_VOFFSET) 4; # in microns
set ::env(FP_PDN_VPITCH) 15
set ::env(FP_PDN_HOFFSET) 4
set ::env(FP_PDN_HPITCH) 15
This reduces the core utilization down to 10% and the PDN vertical and horizontal stripe pitches down to 15um.
m
thanks
I tried this and quit it after 700 iterations
I'm now trying with vpitch and hpitch reduced to 10
when watching those numbers, is there anything to look for in terms of convergence?
I had this exact issue with qflow btw. I had to tweak the power distribution settings to get it to route
a
Adding the following configuration should help it converge in cases where the design is very tiny. This increases the density, bringing the cells closer to each other.
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set ::env(PL_TARGET_DENSITY) 0.9
Very tiny designs can be a bit tricky. Things applied by default like diode insertion, clock tree synthesis, etc. may not be relevant in many cases.
when watching those numbers, is there anything to look for in terms of convergence?
The overflow (OVFL) is what the global placer is trying to get down, so that's what you'd be looking for.
m
changing the target density worked, thanks!
image.png
a
@Matt Venn: Great! Do you mind if we include this example as one of the test designs?
m
no problem at all
a
thanks!
m
I was actually trying to do just an inverter, (without flop), so I could compare it to this: https://twitter.com/matthewvenn/status/1274732696942542851/photo/2
but couldn't get openlane to work without a clock
a
Ah, I see. You can disable clock tree synthesis by setting 
CLOCK_TREE_SYNTH
to 0.
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