ok next step try to create a new design

Question

Matt Venn · Answer

I created the design with this flow tcl design inverter init design config

Matt Venn · Answer

the design is in src inverter v

Matt Venn · Answer

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Matt Venn · Answer

and then flow tcl design inverter fails with this

Matt Venn · Answer

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Ahmed Ghazy · Answer

This is interesting thanks for raising this The thing is that the design is very tiny 2 cells So with a high core utilization see the FP CORE UTIL setting <https github com efabless openlane tree master configuration|here> you get a very tiny layout which is smaller than the default pitch of the power grid You can control both the utilization and the PDN stripe pitches using some configurations variables I suggest setting the utilization to a low value to get a larger layout For example try appending the following into your `designs inverter config tcl` ```set env FP CORE UTIL 10 10 utilization set env FP PDN VOFFSET 4 in microns set env FP PDN VPITCH 15 set env FP PDN HOFFSET 4 set env FP PDN HPITCH 15``` This reduces the core utilization down to 10 and the PDN vertical and horizontal stripe pitches down to 15um

Matt Venn · Answer

thanks

Matt Venn · Answer

I tried this and quit it after 700 iterations

Matt Venn · Answer

I m now trying with vpitch and hpitch reduced to 10

Matt Venn · Answer

when watching those numbers is there anything to look for in terms of convergence

Matt Venn · Answer

I had this exact issue with qflow btw I had to tweak the power distribution settings to get it to route

Ahmed Ghazy · Answer

Adding the following configuration should help it converge in cases where the design is very tiny This increases the density bringing the cells closer to each other ```set env PL TARGET DENSITY 0 9``` Very tiny designs can be a bit tricky Things applied by default like diode insertion clock tree synthesis etc may not be relevant in many cases

Ahmed Ghazy · Answer

gt when watching those numbers is there anything to look for in terms of convergence The overflow OVFL is what the global placer is trying to get down so that s what you d be looking for

Matt Venn · Answer

changing the target density worked thanks

Matt Venn · Answer

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Ahmed Ghazy · Answer

< Matt Venn> Great Do you mind if we include this example as one of the test designs

Matt Venn · Answer

no problem at all

Ahmed Ghazy · Answer

thanks

Matt Venn · Answer

I was actually trying to do just an inverter without flop so I could compare it to this <https twitter com matthewvenn status 1274732696942542851 photo 2>

Matt Venn · Answer

but couldn t get openlane to work without a clock

Ahmed Ghazy · Answer

Ah I see You can disable clock tree synthesis by setting `CLOCK TREE SYNTH` to 0