Matt Venn
07/23/2020, 3:13 PMAhmed Ghazy
07/23/2020, 3:36 PMdesigns/inverter/config.tcl
:
set ::env(FP_CORE_UTIL) 10; # 10 % utilization
set ::env(FP_PDN_VOFFSET) 4; # in microns
set ::env(FP_PDN_VPITCH) 15
set ::env(FP_PDN_HOFFSET) 4
set ::env(FP_PDN_HPITCH) 15
This reduces the core utilization down to 10% and the PDN vertical and horizontal stripe pitches down to 15um.Matt Venn
07/23/2020, 4:05 PMAhmed Ghazy
07/23/2020, 4:27 PMset ::env(PL_TARGET_DENSITY) 0.9
Very tiny designs can be a bit tricky. Things applied by default like diode insertion, clock tree synthesis, etc. may not be relevant in many cases.when watching those numbers, is there anything to look for in terms of convergence?The overflow (OVFL) is what the global placer is trying to get down, so that's what you'd be looking for.
Matt Venn
07/24/2020, 8:41 AMAhmed Ghazy
07/24/2020, 11:36 AMMatt Venn
07/24/2020, 11:37 AMAhmed Ghazy
07/24/2020, 11:39 AMMatt Venn
07/24/2020, 11:42 AMAhmed Ghazy
07/24/2020, 11:55 AMCLOCK_TREE_SYNTH
to 0.