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I'm also getting the or_diodes script failing due to overlap check fail. I've tried setting utilisation down to 10% but still get this error - any ideas on how to debug it?

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<@U0172QZ342D>: That one is different though; it's a rare bug in the detailed placer. The overlaps reported aren't really true, but they cause the flow to stop due to a non-zero exit code. <@U0169AQ41L6> mentioned it's due to a wrong LEF class for the tap cells, but I believe it might go beyond that.

Is it a design you could share so I can reproduce it?

yes, let me just put the changes I made for the asic version into the public repo

just need to copy rtl to src and then run the ./flow vga_clock -init

I also see the SPM design fail if I set the utilization to 15% at the same diode script

Same overlap warning (albeit different cells) as Matt

<@U016HSALFAN> is the "Overlap check failed" warning meaningful and indicative of an error or something that can be ignored?

<@U0172QZ342D>: I could get the design through the flow by setting the core utiliation to 65%; let me know if this helps. <@U0179KL07EH>: See my reply on this issue on the channel; varying the utilization slightly should let you avoid it for now.