I m also getting the or diodes script failing due to overlap

Question

I m also getting the or diodes script failing due to overlap check fail I ve tried setting utilisation down to 10 but still get this error any ideas on how to debug it

Matt Venn · Answer

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Matt Venn · Answer

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Ahmed Ghazy · Answer

< Matt Venn> That one is different though it s a rare bug in the detailed placer The overlaps reported aren t really true but they cause the flow to stop due to a non zero exit code < mehdi> mentioned it s due to a wrong LEF class for the tap cells but I believe it might go beyond that Is it a design you could share so I can reproduce it

Matt Venn · Answer

yes let me just put the changes I made for the asic version into the public repo

Matt Venn · Answer

Matt Venn · Answer

just need to copy rtl to src and then run the flow vga clock init

Matt Venn · Answer

oh and remove the tb v testbenches

Matt Venn · Answer

and here is the config tck

Matt Venn · Answer

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Ahmed Ghazy · Answer

< Matt Venn> Thanks Looking into it

Andy · Answer

I also see the SPM design fail if I set the utilization to 15 at the same diode script

Andy · Answer

Same overlap warning albeit different cells as Matt

Andy · Answer

< Ahmed Ghazy> is the Overlap check failed warning meaningful and indicative of an error or something that can be ignored

Ahmed Ghazy · Answer

< Matt Venn> I could get the design through the flow by setting the core utiliation to 65 let me know if this helps < Andy> See my reply on this issue on the channel varying the utilization slightly should let you avoid it for now

Matt Venn · Answer

Thanks I ll try it on Monday

Matt Venn · Answer

yes it worked

Matt Venn · Answer

thanks