I'm also getting the or_diodes script failing due to overlap check fail. I've tried setting utilisation down to 10% but still get this error - any ideas on how to debug it?
07/24/2020, 11:06 AM
@Matt Venn: That one is different though; it's a rare bug in the detailed placer. The overlaps reported aren't really true, but they cause the flow to stop due to a non-zero exit code. @mehdi mentioned it's due to a wrong LEF class for the tap cells, but I believe it might go beyond that.
Is it a design you could share so I can reproduce it?
07/24/2020, 11:09 AM
yes, let me just put the changes I made for the asic version into the public repo
just need to copy rtl to src and then run the ./flow vga_clock -init
oh and remove the *_tb.v testbenches
and here is the config.tck
07/24/2020, 12:13 PM
@Matt Venn: Thanks. Looking into it.
07/24/2020, 1:17 PM
I also see the SPM design fail if I set the utilization to 15% at the same diode script
Same overlap warning (albeit different cells) as Matt
@Ahmed Ghazy is the "Overlap check failed" warning meaningful and indicative of an error or something that can be ignored?
07/25/2020, 2:06 AM
@Matt Venn: I could get the design through the flow by setting the core utiliation to 65%; let me know if this helps. @Andy: See my reply on this issue on the channel; varying the utilization slightly should let you avoid it for now.