2nd mile-stone in field open-source (efabless open-lane EDA + Google/Sky130 open-process). GitHub is indeed the new RESUME for VLSI industry. Again, let's take a backseat and appreciate/encourage all freshers like @User to do a similar kind of work, by congratulating them @User joined our research project group under VSD Research internship program which runs for 8-weeks. He was supposed to develop flow for standard cell design and characterization using all open-source tools - magic/ngspice, then plug those standard cells into open-source PNR flow by open-lane, and benchmark RTL2GDS flow results. This needed a knowledge, not only of PNR, but device physics, custom layout, DRC/LVS and then (finally) Physical design/STA. All of above using open-source RISC-V design (picorv32a) + open-source EDA tools (open-lane by efabless) + open-process (google+skywater130nm). Here's detailed masterpiece of his work. Its open for review/critics/feedback/comments/usage and everything. Thanks again @User @User @User @User https://github.com/nickson-jose/vsdstdcelldesign

I don't consider this as my achievement alone..this is one for my mentor and guru @Kunal for showing the vision and setting me in the right direction and to the entire Openlane and Skywater team for the amazing work and support..Cheers!! (P.S.: any feedback would be greatly welcome)

May I ask what was the toolchain planned to be use for the timing extraction of the standard cells ?

Hi Ronan, since post routing timing optimization is still a work in progress for openlane, I had used the below tool for SPEF extraction (as suggested by Prof. Shalan) and the analysis was done with spef in openSTA..but that was for the entire design not for std cells

@Ronan BARZIC Above tool was used to extract spef for whole design. For standard cells, there is some work pending on timing characterization. We are waiting for models to be released on public channel

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