https://open-source-silicon.dev logo
#openlane
Title
# openlane
h

Harikumar S

08/31/2020, 11:58 AM
I am working on porting the OSU 45nm Standard Cell Set (FreePDK) for Openlane. While trying to run the flow for the simple example design 'spm', I am encountering the following error during pin access in routing. Error: no ap for clkbuf_0_clk/A Error: no ap for clkbuf_0_clk/Y complete 56 pins Error: pin does not have access point Error: pin does not have access point complete 25 unique inst patterns @@@ dead end inst @@@ dead end inst Error: valid access pattern combination not found. I am also unable to reduce the no. of DRC violations during routing below 2 in spite of using TR14 strategy and a low FP_CORE_UTIL and PL_TARGET_DENSITY. The no. of such errors and DRC violations increases with the complexity of the design. Any idea how to go about solving this issue?
😊 1
a

Ahmed Ghazy

08/31/2020, 3:37 PM
There are pin access issues with some of the cells on OSU; you usually need to exclude some of them. Try to exclude those that TR complains about (by listing them in no_synth.cells). You could also report such pin-related issues on #osu. You could also try the attached tracks file. Also, the layers in the tech LEF must be alternating in orientation, which is not the case by default since li1 was designed to be a horizontal layer.
8 Views