Hi, I have an issue using the openlane flow. Trit...
# openlane
Hi, I have an issue using the openlane flow. TritonRoute reports these errors:
start pin access
complete 100 pins
Error: no ap for clkbuf_3_3_0_clk_i/A
Error: no ap for clkbuf_3_3_0_clk_i/X
Error: no ap for clkbuf_4_8_0_clk_i/A
Error: no ap for clkbuf_4_8_0_clk_i/X
Error: no ap for clkbuf_4_9_0_clk_i/A
Error: no ap for clkbuf_4_9_0_clk_i/X
Error: no ap for clkbuf_3_4_0_clk_i/A
Error: no ap for clkbuf_3_4_0_clk_i/X
Error: no ap for clkbuf_4_0_0_clk_i/A
@tgingold Which std cell library are you using? and can you share this test case?
I use the sky130_fd_sc_hd std cell library. I can share the test case, I will put it in a repo.
Yes please, open an issue here as well.
Thanks. I am also realizing that most (if not all) have a pdk specific configuration file. I will first test more settings before opening the issue on github. But my (simple) design is now on: github.com:tgingold/opentdc.git
@tgingold oh, I see. There is an issue in rc2 when disabling diode_insertion. because the CTS relies that there would be another detailed placement done after it, and it doesn't enforce that. This issue was fixed in the develop and the staging branches and it's coming to master very soon. however, to get your gear going you can add this to the scripts/openroad/or_cts.tcl https://github.com/efabless/openlane/commit/6a7bd8c39f79644a1e153657107f940831101479#diff-bee5547b71274ab7d3d1de4e7ba9de45 Or use DIODE_INSERTION_STRATEGY 1 Also, use ROUTING_STRATEGY 14, it will almost guarantee a 0 DRC design (which is the case with your design)
@tgingold would you mind if I added your design to the openlane public test set?
Yes, you can add my design in the public test. But right now it is still a toy.
Thank you for your help. As a similar work around, I added a pdk specific configuration tcl file from another example. It also works.
I fear that if you create a new design as described in designs/README.md and use the default config file, you will get this problem. Should I create an issue ?
Also, the default test set file is missing. I will create an issue.
Thank you for your help (and thank you for the work on the toolset).
Ok, I see it works differently in the develop branch.
@tgingold Happy to hear it worked, but, yeah this issue will happen with the hs and ms libraries only or if you use DIODE_INSERTION_STRATEGY 0 with any other library, but it was fixed and will be pushed to master very soon. No need to modify the configuration file for the PDK. The cleanest 2 solutions are to either add the lines I mentioned above or use DIODE_INSERTION_STRATEGY 1. So no need to open an issue since it was already fixed in develop and will go to master soon
As for the default test set, it used to be a controlled list in a file, but we moved away from that and made the default test set: all designs under designs/ directory. So, the link in the readme should be removed that's all (and it was removed in develop)