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#openlane
Title
# openlane
a

aryap

09/16/2020, 9:09 PM
unrelated: does openlane have a solution for gate-level simulation?
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Ahmed Ghazy

09/16/2020, 9:23 PM
We used
iverilog
(http://iverilog.icarus.com/) while doing the chips, but it is not part of openlane. There are behavioral verilog modules installed with the PDK you could use for that purpose.
✔️ 1
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aryap

09/16/2020, 10:23 PM
great, thanks!
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Ronan BARZIC

09/17/2020, 10:51 AM
If I'm correct, iverilog still does not support SDF timing retro-annotations - That could make gate-level simulation challenging in complex circuits with a lot of clock gating for example
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aryap

09/18/2020, 8:20 PM
we could just use VCS? but that would defeat the point haha