unrelated: does openlane have a solution for gate-level simulation?

We used

iverilog

(http://iverilog.icarus.com/) while doing the chips, but it is not part of openlane. There are behavioral verilog modules installed with the PDK you could use for that purpose.

great, thanks!

If I'm correct, iverilog still does not support SDF timing retro-annotations - That could make gate-level simulation challenging in complex circuits with a lot of clock gating for example

we could just use VCS? but that would defeat the point haha