@User: This is intentional, yes. For LVS, the schematic you have is a verilog standard-cell-level netlist, so if you use the GDS (or the "mag" view) for the layout, which contains also lower-level devices down to transistors, you will be comparing the schematic to a netlist with many more devices. The line of thought here is that if every block/cell is LVS clean by itself (which should always be the case, otherwise, why would one be using it?), the "internal" netlist details can be abstracted away and LVS can run with only knowledge of how the block connects externally.
For DRC, while using the GDS/"mag" view works for simple standard-cell-only layouts, checking other complex layouts (e.g., IO cells, SRAM blocks) doesn't usually go very well. A similar argument (with some caveats) to the above can also be applied, and running DRC with the maglef view captures all relevant violations that result from routing. If you'd like to experiment with it, simply play with the
MAGTYPE
variable (
mag
vs.
maglef
) set in
scripts/tcl_commands/magic.tcl
.