Hello, I have been running OPENLANE, but when I tried to run the OPENLANE with more than 1 verilog files [top module, sub modules]. The process was terminated at the hierarchy step in synthesis. It could not read the sub modules in the

src

directory The error says:

Top module:  \memory_core

`ERROR: Module `\sram_2_16_1_scn4m_subm' referenced in module `\memory_core' in cell

\dmem' is not part of the design.

in the config.tcl file you need to have VERILOG_FILES set correctly, so it can either be:

set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

or just

set ::env(VERILOG_FILES) "$::env(DESIGN_DIR)/src/*.v"

you may need to change this based on the hierarchy of files you have.

Yes, I have,

set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v]

and it reads the top module successfully. The problem arises with the modules instantiated in it, the Verilog files of these sub modules are separate but in the same directory as that of the top module.

could you share this directory or how it's structured?

openlane /design_name/src

src

>

topmodule.v

,

submodule1.v

,

submodule2.v

...

Well, this is strange. Is there a way you could share the files with me; for me to take a look at my end?

@Wajeh ul hasan: Could you try explicitly listing them in order so as to read the dependencies first? e.g.,

"module1.v module2.v"

etc.

@Ahmed Ghazy Umm.. I do not understand your point. I would have different names of the modules for example ALU, Counter, etc Nomenclature should not have any effect ?