Hi, I am Aireen, a researcher at MERL-UIT. I was r...
# openlanea
Aireen Amir Jalal
10/15/2020, 7:18 AMHi, I am Aireen, a researcher at MERL-UIT. I was running the openlane flow on spm design and ran into this issue at the cts stage. How do I get rid of this error. Previously when I ran the flow, it went pretty smooth without any error. But now, somehow errors have started to appear. Any leads?
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Matt Venn
10/15/2020, 8:03 AMI've seen this with very small designs
Matt Venn
10/15/2020, 8:03 AMor ones with no clock
Matt Venn
10/15/2020, 8:03 AMalso you could have a clock with a different name?
Matt Venn
10/15/2020, 8:04 AMif you have no clock then you can turn off clock tree synthesis
Matt Venn
10/15/2020, 8:04 AMa
Aireen Amir Jalal
10/15/2020, 8:36 AMCheers. Thanks @Matt Venn, the error is resolved.
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Ahmed Ghazy
10/15/2020, 5:37 PM@Aireen Amir Jalal: I can see that this is spm. The output above is not normal; spm does have sinks. This is what it should be showing from a successful run:
Copy code
Net "clk" found
Initializing clock net for : "clk"
Clock net "clk" has 64 sinks
TritonCTS found 1 clock nets.m
Matt Venn
10/16/2020, 1:26 PMgood catch, didn't see it was for the spm design
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Aireen Amir Jalal
10/16/2020, 3:00 PMyes @Ahmed Ghazy, the spm design definitely has sinks, the error was something else, which I figured out later and managed to get rid off. some of the files in openroad directory, got hidden from the flow as they were opened in other tabs. So the steps above cts weren't successful somehow.
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