https://open-source-silicon.dev logo
#openlane
Title
# openlane
a

Aireen Amir Jalal

10/15/2020, 7:18 AM
Hi, I am Aireen, a researcher at MERL-UIT. I was running the openlane flow on spm design and ran into this issue at the cts stage. How do I get rid of this error. Previously when I ran the flow, it went pretty smooth without any error. But now, somehow errors have started to appear. Any leads?
m

Matt Venn

10/15/2020, 8:03 AM
I've seen this with very small designs
or ones with no clock
also you could have a clock with a different name?
if you have no clock then you can turn off clock tree synthesis
a

Aireen Amir Jalal

10/15/2020, 8:36 AM
Cheers. Thanks @Matt Venn, the error is resolved.
a

Ahmed Ghazy

10/15/2020, 5:37 PM
@Aireen Amir Jalal: I can see that this is spm. The output above is not normal; spm does have sinks. This is what it should be showing from a successful run:
Copy code
Net "clk" found
 Initializing clock net for : "clk"
 Clock net "clk" has 64 sinks
 TritonCTS found 1 clock nets.
I suspect that something went wrong with synthesis. Could you share your synthesis log?
m

Matt Venn

10/16/2020, 1:26 PM
good catch, didn't see it was for the spm design
a

Aireen Amir Jalal

10/16/2020, 3:00 PM
yes @Ahmed Ghazy, the spm design definitely has sinks, the error was something else, which I figured out later and managed to get rid off. some of the files in openroad directory, got hidden from the flow as they were opened in other tabs. So the steps above cts weren't successful somehow.
👍 1