Wajeh ul hasan

10/22/2020, 11:59 AM
Hello, I was running the design with the memory module set as a black_box by adding the below two variables in the ``l script:
set ::env(VERILOG_FILES_BLACKBOX) $::env(OPENLANE_ROOT)/designs/design_name/src/abc.v
However, after synthesis I realized that although there were no errors but no mapping was done and an empty netlist was generated. I went through the log files and observed that it is not creating anything. It had the following the messages:
Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module memory_core:
created 0 $alu and 0 $macc cells
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
`Extracting gate netlist of module `\memory_core' to
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map