Matt A10/22/2020, 12:59 PM
Amr Gouhar10/22/2020, 1:06 PM
the other is found in
. The timing reports under synthesis, should give you a perspective on what clock frequency to use when the design gets out eventually (there is a new feature in the coming release that calculates that for you). Then you have the antenna violations produced under
at the end of that document you could see the number of violating pins and nets, you can search for
to see what parameters are violated in which nets. Finally, you get the LVS reports, which could be found under
which tells you if the final layout have any mismatches with the original netlist (this happens in case of a short, for example). And that's that, I guess.