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#openlane
Title
# openlane
a

aryap

10/29/2020, 2:00 AM
ok now i get a segfault running
gen_pdn
. This is definitely related to my config I'm guessing: ``````
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Notice 0:     Created 11 technology layers
Notice 0:     Created 25 technology vias
Notice 0:     Created 440 library cells
Notice 0: Finished LEF file:  /openLANE_flow/designs/250/runs/debug/tmp/merged_unpadded.lef
Notice 0: 
Reading DEF file: /openLANE_flow/designs/250/runs/debug/tmp/floorplan/pdn.def
Notice 0: Design: fpga_250
Notice 0: 		Created 100000 Insts
Notice 0:     Created 37 pins.
Notice 0:     Created 142032 components and 284390 component-terminals.
Notice 0:     Created 2 special nets and 0 connections.
Notice 0:     Created 35 nets and 32 connections.
Notice 0: Finished DEF file: /openLANE_flow/designs/250/runs/debug/tmp/floorplan/pdn.def
[INFO] [PDNG-0016] Power Delivery Network Generator: Generating PDN
[INFO] [PDNG-0016]   config: /openLANE_flow/designs/250/src/pdn.tcl
[INFO] [PDNG-0008] Design Name is fpga_250
[INFO] [PDNG-0009] Reading technology data
[INFO] [PDNG-0011] ****** INFO ******
Type: stdcell, grid
    Core Rings
      Layer: met4 -  width: 20.000  spacing: 5.000  core_offset: 20.000 
      Layer: met5 -  width: 20.000  spacing: 5.000  core_offset: 20.000 
    Stdcell Rails
      Layer: met1 -  width: 0.480  pitch: 2.720  offset: 0.000 
    Straps
      Layer: met4 -  width: 1.600  pitch: 153.600  offset: 16.320 
      Layer: met5 -  width: 1.600  pitch: 153.180  offset: 16.650 
    Connect: {met1 met4} {met4 met5}
Type: macro, macro_1
    Instance: my_mac
    Straps
    Connect: {met4_PIN_ver met4}
[INFO] [PDNG-0012] **** END INFO ****
[INFO] [PDNG-0013] Inserting stdcell grid - grid
[INFO] [PDNG-0010] Inserting macro grid for 1 macros
[INFO] [PDNG-0034]   - grid for instance my_mac
[INFO] [PDNG-0015] Writing to database
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/new_pdn.tcl |& tee >&@stdout /openLANE_flow/designs/250/runs/debug/logs/floorplan/pdn.log"
[ERROR]: Last 10 lines:
child killed: segmentation violation
i force-skip CTS because there is no clock. my config.tcl and pdn.tcl are attached
my script is now
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add_lefs -src /openLANE_flow/designs/250_mac/runs/cluster_750_750_0.3/results/magic/mac_cluster.lef

run_synthesis

init_floorplan
place_io
global_placement_or

add_macro_placement my_mac 0 0

manual_macro_placement
tap_decap_or

run_placement
run_cts
gen_pdn
run_routing
run_magic
run_magic_spice_export
run_magic_drc
run_lvs
run_antenna_check
please help 😥
a

Amr Gouhar

10/29/2020, 12:45 PM
I see for the macro pdn.tcl, you have a connect {met4_PIN_ver met4} which is telling pdngen to connect metal 4 vertical pins to metal 4. I think what you want to do is change that to met5 (depends on what you want to accomplish tho). Also, you run
run_placement
after doing global and manual macro placement, which will overwrite everything you've done so far. What you want to do is run
detail_placement
and then pick up the flow steps from
run_placement
but excluding it. (this won't cause a crash).
a

aryap

10/29/2020, 5:46 PM
thank you!
i'm not sure if this is right yet though. now
or_diodes.tcl
fails:
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Warning: Overlap check failed (32).
 ANTENNA_my_mac_A1[0] overlaps my_mac
 ANTENNA_my_mac_B1[0] overlaps my_mac
 ANTENNA_my_mac_A1[1] overlaps my_mac
 ANTENNA_my_mac_B1[1] overlaps my_mac
 ANTENNA_my_mac_A1[2] overlaps my_mac
 ANTENNA_my_mac_B1[2] overlaps my_mac
 ANTENNA_my_mac_A1[3] overlaps my_mac
 ANTENNA_my_mac_B1[3] overlaps my_mac
 ANTENNA_my_mac_A1[4] overlaps my_mac
 ANTENNA_my_mac_B1[4] overlaps my_mac
 ANTENNA_my_mac_A1[5] overlaps my_mac
 ANTENNA_my_mac_B1[5] overlaps my_mac
 ANTENNA_my_mac_A1[6] overlaps my_mac
 ANTENNA_my_mac_B1[6] overlaps my_mac
 ANTENNA_my_mac_A1[7] overlaps my_mac
 ANTENNA_my_mac_B1[7] overlaps my_mac
 ANTENNA_my_mac_A0[0] overlaps my_mac
 ANTENNA_my_mac_B0[0] overlaps my_mac
 ANTENNA_my_mac_A0[1] overlaps my_mac
 ANTENNA_my_mac_B0[1] overlaps my_mac
 ANTENNA_my_mac_A0[2] overlaps my_mac
 ANTENNA_my_mac_B0[2] overlaps my_mac
 ANTENNA_my_mac_A0[3] overlaps my_mac
 ANTENNA_my_mac_B0[3] overlaps my_mac
 ANTENNA_my_mac_A0[4] overlaps my_mac
 ANTENNA_my_mac_B0[4] overlaps my_mac
 ANTENNA_my_mac_A0[5] overlaps my_mac
 ANTENNA_my_mac_B0[5] overlaps my_mac
 ANTENNA_my_mac_A0[6] overlaps my_mac
 ANTENNA_my_mac_B0[6] overlaps my_mac
 ANTENNA_my_mac_A0[7] overlaps my_mac
 ANTENNA_my_mac_B0[7] overlaps my_mac
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_diodes.tcl |& tee >&@stdout /openLANE_flow/designs/250/runs/debug/logs/placement/diodes.log"
[ERROR]: Last 10 lines:
child process exited abnormally
is there a working example of macro placement available that I could work from instead of all this guessing and checking?
conscious that i've bugged you once a day for like 5 days
a

Amr Gouhar

10/29/2020, 5:57 PM
This should be available with the SoC release, soon.. But this could work as an example:
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package require openlane
set script_dir [file dirname [file normalize [info script]]]
set design_name SOME_DESIGN_NAME
prep -design $script_dir -tag $design_name -run_path $script_dir/../../runs/ -overwrite
set save_path $script_dir/../../../

set lefs 	 $::env(EXTRA_LEFS)
puts "LEFS: $lefs"
add_lefs -src $lefs

run_synthesis
init_floorplan_or
place_io
global_placement_or
add_macro_placement SOME_MACRO_NAME 5 10
manual_macro_placement
detailed_placement
try_catch $::env(SCRIPTS_DIR)/mark_component_fixed.sh "SOME_MACRO_NAME" $::env(CURRENT_DEF)
tap_decap_or
detailed_placement
gen_pdn
run_routing

if { $::env(DIODE_INSERTION_STRATEGY) == 2 } {
    run_magic_antenna_check; # produces a report of violators; extraction!
    heal_antenna_violators; # modifies the routed DEF
}

run_magic    
save_views       -lef_path $::env(magic_result_file_tag).lef \
                 -def_path $::env(tritonRoute_result_file_tag).def \
                 -gds_path $::env(magic_result_file_tag).gds \
                 -mag_path $::env(magic_result_file_tag).mag \
                 -save_path $save_path \
                 -tag $::env(RUN_TAG)

run_magic_drc

run_magic_spice_export
run_lvs

run_antenna_check; # to verify the above and get a final report
with the macro section in the pdn.tcl (this should be changed of course to what suits the design):
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pdngen::specify_grid macro {
    instance "SOME_MACRO_NAME"
    power_pins "SOME_PIN"
    ground_pins "ANOTHER_PIN"
    blockages "li1 met1 met2 met3 met4"
    straps { 
    } 
    connect {{met4_PIN_ver met5}}
}
a

aryap

10/29/2020, 8:24 PM
thanks! Ok I've tried the new script on rc3 and the develop branch. nothing seems to work. 1. i tried your script more or less as given:
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package require openlane
set script_dir [file dirname [file normalize [info script]]]
set design_name fpga_250
prep -design $script_dir -tag $design_name -run_path $script_dir/runs -overwrite
set save_path $script_path/save

#set lefs $::env(EXTRA_LEFS)
add_lefs -src /openLANE_flow/designs/250_mac/runs/cluster_750_750_0.3/results/magic/mac_cluster.lef

run_synthesis

init_floorplan_or
place_io
global_placement_or  ;# <-- fails here

add_macro_placement my_mac 0 0
manual_macro_placement
detailed_placement

puts "current def is $::env(CURRENT_DEF)"
try_catch $::env(SCRIPTS_DIR)/mark_component_fixed.sh my_macro $::env(CURRENT_DEF)

tap_decap_or
detailed_placement

gen_pdn
run_routing

if { $::env(DIODE_INSERTION_STRATEGY) == 2 } {
    run_magic_antenna_check; # produces a report of violators; extraction!
    heal_antenna_violators; # modifies the routed DEF
}

run_magic
save_views      -lef_path $::env(magic_result_file_tag).lef \
                -def_path $::env(tritonRoute_result_file_tag).def \
                -gds_path $::env(magic_result_file_tag).gds \
                -mag_path $::env(magic_result_file_tag).mag \
                -save_path $save_path \
                -tag $::env(RUN_TAG)

run_magic_drc
run_magic_spice_export
run_lvs
run_antenna_check
but it fails at
global_placement_or
with
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[INFO] IdealBinCnt = 9
[INFO] TotalBinArea = 11248041513600
[INFO] BinCnt = (2, 2)
[INFO] BinSize = (1676930, 1676880)
[INFO] NumBins = 4
[ERROR]  (REPL-0)
Error: RePlAce terminated with errors.
[ERROR]: Failure in global placement

    while executing
"global_placement_or"
    (file "/openLANE_flow/designs/250/tile.tcl" line 15)
child process exited abnormally
    while executing
2. I was previously doing
init_floorplan
instead of
init_floorplan_or
and that gets further on rc3; it fails at the same point on develop as before. on rc3 i get this again:
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Warning: Placed in rows check failed (32).
 ANTENNA_my_mac_A1[0]
 ANTENNA_my_mac_B1[0]
 ANTENNA_my_mac_A1[1]
 ANTENNA_my_mac_B1[1]
 ANTENNA_my_mac_A1[2]
 ANTENNA_my_mac_B1[2]
 ANTENNA_my_mac_A1[3]
 ANTENNA_my_mac_B1[3]
 ANTENNA_my_mac_A1[4]
 ANTENNA_my_mac_B1[4]
 ANTENNA_my_mac_A1[5]
 ANTENNA_my_mac_B1[5]
 ANTENNA_my_mac_A1[6]
 ANTENNA_my_mac_B1[6]
 ANTENNA_my_mac_A1[7]
 ANTENNA_my_mac_B1[7]
 ANTENNA_my_mac_A0[0]
 ANTENNA_my_mac_B0[0]
 ANTENNA_my_mac_A0[1]
 ANTENNA_my_mac_B0[1]
 ANTENNA_my_mac_A0[2]
 ANTENNA_my_mac_B0[2]
 ANTENNA_my_mac_A0[3]
 ANTENNA_my_mac_B0[3]
 ANTENNA_my_mac_A0[4]
 ANTENNA_my_mac_B0[4]
 ANTENNA_my_mac_A0[5]
 ANTENNA_my_mac_B0[5]
 ANTENNA_my_mac_A0[6]
 ANTENNA_my_mac_B0[6]
 ANTENNA_my_mac_A0[7]
 ANTENNA_my_mac_B0[7]
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_diodes.tcl |& tee >&@stdout /openLANE_flow/designs/250/runs/fpga_250/logs/placement/diodes.log"
[ERROR]: Last 10 lines:
child process exited abnormally

[ERROR]: Please check openroad  log file
[ERROR]: Dumping to /openLANE_flow/designs/250/runs/fpga_250/error.log

    while executing
"try_catch openroad -exit $::env(SCRIPTS_DIR)/openroad/or_diodes.tcl |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/placement/diodes.log"
    (procedure "ins_diode_cells" line 5)
    invoked from within
"ins_diode_cells"
    (procedure "run_routing" line 10)
    invoked from within
"run_routing"
    (file "/openLANE_flow/designs/250/tile.tcl" line 33)
i tried moving the macro to
add_macro_placement my_mac 1 1
and the same things happen
a

Amr Gouhar

10/30/2020, 3:24 PM
@aryap: I'd go with the Antenna placement errors version and reduce the FP_CORE_UTIL and PL_TARGET_DENSITY
a

aryap

10/30/2020, 6:37 PM
Thanks @Amr Gouhar. I've tried relative sizing with various CORE_UTIL, TARGET_DENSITY VALUES= (5, 0.5), (2, 0.1), (1, 0.05) and i always encounter that error. then I tried "absolute" sizing with a huge die (10000x10000).
i'll PR with my design
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non_group_cell_region_assign done ..
 - - - - - - - - - - - - - - - - - - - - - - - - 
 can't insert center cell !! 
 cell_name : my_mac
 non_group_cell_placement done ..
I noticed this on a run that fails with the antenna placement errors
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