drr
11/14/2020, 12:20 AMAll nwells must contain metal-connected N+ taps (nwell.4)
I am not designing my own cells or modifying the ones provided in the Skywater libs. Does anyone know how these are caused or how to address them? My design is all HDL. This is with rc4
of the open lane repo, running in docker.Riking28
11/14/2020, 4:08 AMDIODE_INSERTION_STRATEGY
drr
11/14/2020, 6:10 AMRiking28
11/14/2020, 5:33 PMAmr Gouhar
11/16/2020, 4:25 PM