i'm also trying to place a macro using

::env(MACRO_PLACEMENT_CFG)

. my macro makes it intact through synthesis, but fails during

replace

with

Design name: mac_tile
Traceback (most recent call last):
  File "/openLANE_flow/scripts/manual_macro_place.py", line 115, in <module>
    assert not macros, ("Macros not found:", macros)
AssertionError: ('Macros not found:', {'macaroni': ['5000', '5000', 'N']}

indeed, the instance is missing from

tmp/merged.lef

? but it it appears in synthesis fine and i don't see any errors emitted anywhere. any ideas?

That error was when I had the name of the macro wrong. It needs to be the name of the instance, you can look in the DEF.

no, it's missing from the DEF entirely

Does it appear in the final yosys report ?

yes, hence my confusion. here is the final yosys report:

19222 === mac_tile ===
19223 
19224    Number of wires:              26386
19225    Number of wire bits:          27158
19226    Number of public wires:        5622
19227    Number of public wire bits:    6394
19228    Number of memories:               0
19229    Number of memory bits:            0
19230    Number of processes:              0
19231    Number of cells:              27467
19232      mac_cluster                     1
19233      sky130_fd_sc_hd__a21o_4      2331
19234      sky130_fd_sc_hd__a21oi_4     1168
19235      sky130_fd_sc_hd__a22oi_4        1
19236      sky130_fd_sc_hd__buf_1       4148
19237      sky130_fd_sc_hd__dfxtp_4     5536
19238      sky130_fd_sc_hd__inv_8       1169
19239      sky130_fd_sc_hd__nor2_4      8742
19240      sky130_fd_sc_hd__nor3_4      3200
19241      sky130_fd_sc_hd__o21ai_4        1
19242      sky130_fd_sc_hd__or2_4          6
19243      transmission_gate            1164
19244 
19245    Area for cell type \mac_cluster is unknown!
19246    Area for cell type \transmission_gate is unknown!
19247 
19248    Chip area for module '\mac_tile': 364918.736000
19249 
19250 32. Executing Verilog backend.
19251 Dumping module `\mac_tile'.

And you specified

EXTRA_LEFS

and

EXTRA_GDS_FILES

in your config ?

yes...

I guess try reading the whole backlog of the run ... sometimes it throws error that don't stop the flow and you have to read the whole thing to see where things went bad.

yeah, but nothing seems to go wrong in synthesis (the output verilog instantiates the right thing), and replace.log has no "error" in it (aside from the algorithm's internal error count print out)

verilog2def

is what creates the initial DEF from the synthesis results AFAIK.

ok i will check that. thanks

does

floorplan/verilog2def_openroad.def

has your macro ?

checking...

What line is 165106 ?

it's a parameter