i m also trying to place a macro using ` env MACRO PLACEMENT

Question

i m also trying to place a macro using ` env MACRO PLACEMENT CFG ` my macro makes it intact through synthesis but fails during `replace` with ```Design name mac tile Traceback most recent call last File openLANE flow scripts manual macro place py line 115 in lt module gt assert not macros Macros not found macros AssertionError Macros not found macaroni 5000 5000 N ``` indeed the instance is missing from `tmp merged lef` but it it appears in synthesis fine and i don t see any errors emitted anywhere any ideas

aryap · Answer

sorry more precisely the instance is missing from the input `def` `tmp placement replace def`

tnt · Answer

That error was when I had the name of the macro wrong It needs to be the name of the instance you can look in the DEF

aryap · Answer

no it s missing from the DEF entirely

tnt · Answer

Does it appear in the final yosys report

aryap · Answer

yes hence my confusion here is the final yosys report ```19222 === mac tile === 19223 19224 Number of wires 26386 19225 Number of wire bits 27158 19226 Number of public wires 5622 19227 Number of public wire bits 6394 19228 Number of memories 0 19229 Number of memory bits 0 19230 Number of processes 0 19231 Number of cells 27467 19232 mac cluster 1 19233 sky130 fd sc hd a21o 4 2331 19234 sky130 fd sc hd a21oi 4 1168 19235 sky130 fd sc hd a22oi 4 1 19236 sky130 fd sc hd buf 1 4148 19237 sky130 fd sc hd dfxtp 4 5536 19238 sky130 fd sc hd inv 8 1169 19239 sky130 fd sc hd nor2 4 8742 19240 sky130 fd sc hd nor3 4 3200 19241 sky130 fd sc hd o21ai 4 1 19242 sky130 fd sc hd or2 4 6 19243 transmission gate 1164 19244 19245 Area for cell type mac cluster is unknown 19246 Area for cell type transmission gate is unknown 19247 19248 Chip area for module mac tile 364918 736000 19249 19250 32 Executing Verilog backend 19251 Dumping module ` mac tile ```

aryap · Answer

the module is `mac cluster` and the instance is `macaroni`

tnt · Answer

And you specified `EXTRA LEFS` and `EXTRA GDS FILES` in your config

aryap · Answer

yes

aryap · Answer

i m triple checking these again

tnt · Answer

I guess try reading the whole backlog of the run sometimes it throws error that don t stop the flow and you have to read the whole thing to see where things went bad

aryap · Answer

yeah but nothing seems to go wrong in synthesis the output verilog instantiates the right thing and replace log has no error in it aside from the algorithm s internal error count print out

aryap · Answer

all the referenced lef files exist and are accessible

tnt · Answer

`verilog2def` is what creates the initial DEF from the synthesis results AFAIK

aryap · Answer

ok i will check that thanks

tnt · Answer

does `floorplan verilog2def openroad def` has your macro

tnt · Answer

` tmp floorplan `

aryap · Answer

checking

aryap · Answer

ok i think i found it

aryap · Answer

`1763 Error openLANE flow designs 250 mac tile runs debug results synthesis mac tile synthesis v line 165106 syntax error unexpected `

aryap · Answer

i think this might not support newer verilog syntax

aryap · Answer

it complains about this line ``` mac cluster MAC ACC WIDTH 32 sb00000000000000000000000000100000 MAC CONF WIDTH 32 sb00000000000000000000000000000100 MAC INT WIDTH 32 sb00000000000000000000000000101000 MAC MIN WIDTH 32 sb00000000000000000000000000001000 MAC MULT WIDTH 32 sb00000000000000000000000000010000 macaroni redacted ```

aryap · Answer

interesting it doesn t make sense to parameterise the black box but yosys includes it anyway

aryap · Answer

it also doesn t make sense to break in parsing it

tnt · Answer

What line is 165106

aryap · Answer

it s a parameter

aryap · Answer

<https github com efabless openlane issues 95> describes it

aryap · Answer

thanks