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a

aryap

11/17/2020, 7:12 AM
i'm also trying to place a macro using
::env(MACRO_PLACEMENT_CFG)
. my macro makes it intact through synthesis, but fails during
replace
with
Copy code
Design name: mac_tile
Traceback (most recent call last):
  File "/openLANE_flow/scripts/manual_macro_place.py", line 115, in <module>
    assert not macros, ("Macros not found:", macros)
AssertionError: ('Macros not found:', {'macaroni': ['5000', '5000', 'N']}
indeed, the instance is missing from
tmp/merged.lef
? but it it appears in synthesis fine and i don't see any errors emitted anywhere. any ideas?
sorry, more precisely the instance is missing from the input
def
,
tmp/placement/replace.def
t

tnt

11/17/2020, 7:14 AM
That error was when I had the name of the macro wrong. It needs to be the name of the instance, you can look in the DEF.
a

aryap

11/17/2020, 7:14 AM
no, it's missing from the DEF entirely
t

tnt

11/17/2020, 7:15 AM
Does it appear in the final yosys report ?
a

aryap

11/17/2020, 7:15 AM
yes, hence my confusion. here is the final yosys report:
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19222 === mac_tile ===
19223 
19224    Number of wires:              26386
19225    Number of wire bits:          27158
19226    Number of public wires:        5622
19227    Number of public wire bits:    6394
19228    Number of memories:               0
19229    Number of memory bits:            0
19230    Number of processes:              0
19231    Number of cells:              27467
19232      mac_cluster                     1
19233      sky130_fd_sc_hd__a21o_4      2331
19234      sky130_fd_sc_hd__a21oi_4     1168
19235      sky130_fd_sc_hd__a22oi_4        1
19236      sky130_fd_sc_hd__buf_1       4148
19237      sky130_fd_sc_hd__dfxtp_4     5536
19238      sky130_fd_sc_hd__inv_8       1169
19239      sky130_fd_sc_hd__nor2_4      8742
19240      sky130_fd_sc_hd__nor3_4      3200
19241      sky130_fd_sc_hd__o21ai_4        1
19242      sky130_fd_sc_hd__or2_4          6
19243      transmission_gate            1164
19244 
19245    Area for cell type \mac_cluster is unknown!
19246    Area for cell type \transmission_gate is unknown!
19247 
19248    Chip area for module '\mac_tile': 364918.736000
19249 
19250 32. Executing Verilog backend.
19251 Dumping module `\mac_tile'.
the module is
mac_cluster
and the instance is
macaroni
t

tnt

11/17/2020, 7:16 AM
And you specified
EXTRA_LEFS
and
EXTRA_GDS_FILES
in your config ?
a

aryap

11/17/2020, 7:17 AM
yes...
i'm triple checking these again
t

tnt

11/17/2020, 7:17 AM
I guess try reading the whole backlog of the run ... sometimes it throws error that don't stop the flow and you have to read the whole thing to see where things went bad.
a

aryap

11/17/2020, 7:18 AM
yeah, but nothing seems to go wrong in synthesis (the output verilog instantiates the right thing), and replace.log has no "error" in it (aside from the algorithm's internal error count print out)
all the referenced lef files exist and are accessible
t

tnt

11/17/2020, 7:20 AM
verilog2def
is what creates the initial DEF from the synthesis results AFAIK.
a

aryap

11/17/2020, 7:21 AM
ok i will check that. thanks
t

tnt

11/17/2020, 7:21 AM
does
floorplan/verilog2def_openroad.def
has your macro ?
/tmp/floorplan/...
a

aryap

11/17/2020, 7:21 AM
checking...
ok i think i found it
1763 Error: /openLANE_flow/designs/250_mac_tile/runs/debug/results/synthesis/mac_tile.synthesis.v, line 165106 syntax error, unexpected '.'.
i think this might not support newer verilog syntax
it complains about this line:
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mac_cluster #(
    .MAC_ACC_WIDTH(32'sb00000000000000000000000000100000),
    .MAC_CONF_WIDTH(32'sb00000000000000000000000000000100),
    .MAC_INT_WIDTH(32'sb00000000000000000000000000101000),
    .MAC_MIN_WIDTH(32'sb00000000000000000000000000001000),
    .MAC_MULT_WIDTH(32'sb00000000000000000000000000010000)
  ) macaroni ( /* redacted */ );
interesting. it doesn't make sense to parameterise the black box but yosys includes it anyway
it also doesn't make sense to break in parsing it
t

tnt

11/17/2020, 7:40 AM
What line is 165106 ?
a

aryap

11/17/2020, 7:42 AM
it's a parameter
thanks!
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