open-source-silicon.dev

"make user_proj_example" in my repository<https://github.com/thesourcerer8/caravel-stdcelllib-stdcells/> gives those errors:
 [PROC] Begin Extracting Macro Cells ...
[ERROR] Cannot find any macros in this design.
 (MAPL-3)
[ERROR]: during executing: "openroad -exit /openLANE_flow/scripts/openroad/or_basic_mp.tcl |&amp; tee &gt;&amp;@stdout /project/openlane/user_proj_example/runs/user_proj_example/logs/placement/basic_mp.log"
[ERROR]: Exit code: 1
Any ideas?

<@U016HSAH6AE>: I don't understand what do you need these includes for:
```# Adding the standard cells into OpenLane:
set ::env(EXTRA_LEFS) [glob $script_dir/../../cells/lef/*.lef]
#set lefs [glob $script_dir/../../cells/lef/*.lef]
#add_lefs -src $lefs

set ::env(EXTRA_LIBS) [glob $script_dir/../../cells/lib/libres*.lib]

set ::env(EXTRA_GDS_FILES)  [glob $script_dir/../../cells/gds/*.gds]```
since these files are already present in openlane (the std cells). What library are you using? Because this naming `AND2X1` doesn't follow any opensource pdk that I know of. You might want to check this: <https://github.com/efabless/openlane/tree/master/designs/digital_pll_sky130_fd_sc_hd> as an example of using the cells directly.

I am developing StdCellLib (<https://github.com/thesourcerer8/StdCellLib|https://github.com/thesourcerer8/StdCellLib>), and generated a standard cell library for SKY130, based on the netlists of the OSU180 library: <https://pdk.libresilicon.com/dist/|https://pdk.libresilicon.com/dist/> <https://pdk.libresilicon.com/dist/StdCellLib_20201106_SKY130/Catalog/buildreport.html|https://pdk.libresilicon.com/dist/StdCellLib_20201106_SKY130/Catalog/buildreport.html>

For the first tests, I just want to place each cell once into the user-space of caravel and connect each cell to the IOs.

The AND2X1 naming comes from the OSU180 netlists, but the cells are generated for SKY130

I have put my cells into the new directory "caravel/cells" inside my caravel based design since I didnt wanted to get my cells included in openlane due to the near deadline

<@U01634FSETZ>: So do you have any ideas?

<@U016HSAH6AE>: I will try to reproduce your experiment later today and report to you if I reach anywhere.

I just found problems in my LEF files and will to fix them first. Stay tuned.

<https://pdk.libresilicon.com/caravel-build.html|https://pdk.libresilicon.com/caravel-build.html> this is the complete log, by the way

<@U01634FSETZ>: Hmm, I currently believe that those LEF file issues are most likely not causing this "Cannot find any macros in this design" error, which is issued by bin/openlane . So please try to reproduce my experiment now.

<@U016HSAH6AE> I've been having this same issue for a few days now