open-source-silicon.dev

What are people seeing for typical runtimes on openlane? Our design is ~8.5k cells and takes a couple hours on a mid range desktop.

About 15-20 min for a 10k cell design on a Ryzen 3700X with 32G RAM.

Tried out different design sizes on Ryzen 3 2200G, 16GB RAM . 10k-50k cell designs run for couple of hours. 200k-500k cell designs and above never finish due to different errors. :D

<@U017REC9K36>: maybe, you need to loosen the `FP_CORE_UTIL`, `PL_TARGET_DENSITY`, and `CLOCK_PERIOD`  a bit. The design maybe too congested but not congested enough for fastroute to fail.

Also, this sheet should give you a sense of the runtimes: <https://github.com/efabless/openlane/blob/master/regression_results/benchmark_results/SW_HD.csv>
*this is runtime to finish routing*