Getting the design LVS clean is mandatory, although you may have to fiddle with the combinations of what libraries you are including, what's considered a black box, etc. DRC should be clean but will require forcing the I/O pads and SRAM blocks to be abstract views, since magic cannot read the GDS of the former properly, and does not try to capture all the special exception DRC rules of the latter. For antenna rule checks, I am recommending keeping the violations within 2x of the rule---these are rules that affect yield, and the rules are written for production chips to keep yield losses very low. For a shuttle run project you can get by with much lower yield. SkyWater does not check antenna rules during tape-in.