Did anyone manage to get a DRC/LVS/antenna clean design?
Are there any errors we should ignore?
11/27/2020, 9:56 AM
I would love an answer to this question @Tim Edwards
11/27/2020, 2:29 PM
Getting the design LVS clean is mandatory, although you may have to fiddle with the combinations of what libraries you are including, what's considered a black box, etc. DRC should be clean but will require forcing the I/O pads and SRAM blocks to be abstract views, since magic cannot read the GDS of the former properly, and does not try to capture all the special exception DRC rules of the latter. For antenna rule checks, I am recommending keeping the violations within 2x of the rule---these are rules that affect yield, and the rules are written for production chips to keep yield losses very low. For a shuttle run project you can get by with much lower yield. SkyWater does not check antenna rules during tape-in.
11/27/2020, 2:38 PM
can you further explain 'keeping violations with 2x of the rule'?
And how about the magic DRC errors? like: All nwells must contain metal-connected N+ taps (nwell.4) or Min area of metal1 holes > 0.14um^2 (met1.7)
11/27/2020, 10:32 PM
The antenna rule checker gives a numeric value and the threshold. Tim is saying you can safely double the threshold if you're fine with some dead chips