Is there some README file or guide I can follow to know how to set properly the parameters such as _FP_SIZING, DIE_AREA_ or _DESIGN_IS_CORE_ in the "_openlane/user_project_wrapper/config.tcl_" file. I am seeing an error when running "_make user_project_wrapper_" during yosys execution doing after step 21.3 :

21.3 Executing FLATTEN pass (flatten design).
[ERROR] during executing "yosys -c /openLANE_flow/scripts/synth.tcl -l /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/synthesis/yosys.log |&...

I tried increasing the _DIE_AREA_ to "0 0 2920 3520" but still see the same error so I was wondering if you could point me in the right direction in order to know how should I determine the rest of variables to be able to make progress. Looking at the README file I cannot see what approach should I follow. Thanks.

what is the content of

logs/synthesis/yosys.log

?

Given that the log is pretty big, I uploaded it to my Google Drive: https://drive.google.com/file/d/1JHYhdyi-x2OMVW0pRZb3P00pb4P0kYj8/view?usp=sharing I see no errors on the log.

Access Denied ...

Thats weird, can you try again?

Given the abrupt end my guess is you ran out of RAM and it crashed or got killed.

Ok, I hoped that with 4GB it was enough

Looking at the design, you have some memories in there ..

Aprox. 150Kbits

yeah, that doesn't stand a chance.

So either I reduce the memory sizes or I increase the RAM, am I wrong?

That doesn't stand a chance of fitting in the area you have.

Ok, I will work on decreasing the amount of memory I have. Is there some arpox. number you recommend? Thank you so much for your help during this two days, I know its sunday so I really appreciate it

you can try to use the optimized DFFRAM blocks, they are manually created net list to reduce area.

I will take a look, thanks!!