Matt Venn

12/04/2020, 12:06 PM
@User following the install instructions for openlane I can run make test and get a clean result including LVS. However, there are no cells in the extracted spice, and the GDS only contains routing. There are many log messages about standard cells not being found
in open_pdks I tried re-running make and make install local
and now I get gds and spice files with the devices present
so I think there is a problem with the openlane makefile
Something crucial here is that LVS will pass even if there is nothing execpt wires inside the gds
😔 1
I can't understand how that is possible

Mitch Bailey

12/04/2020, 1:24 PM
@Matt Venn I looks like it might be when netgen can't find any devices in one or both of the 2 subcircuits being compared, that it will just check to make sure the pins match. In essence, assume it's a blackbox.

Ahmed Ghazy

12/04/2020, 1:43 PM
@Matt Venn: As @Mitch Bailey said, it's using the abstract views for LVS.
@Matt Venn: I will try a fresh install now.

Hanssel Enrique Morales Norato

12/04/2020, 3:38 PM
I told this pre-deadline and no one paid attention to me
@Matt Venn The answer to the LVS thing from @Amr Gouhar was "Actually no, since lvs is done on a spice netlist vs a verilog netlist."
which doesn't make sense because LVS literally means layout vs schematic, not schematic vs RTL.

Ahmed Ghazy

12/04/2020, 3:47 PM
@Hanssel Enrique Morales Norato: NETGEN can compare spice/verilog Vs. spice/verilog, so a spice netlist is extracted from the routed layout using magic and is used in the comparison.