This small design has 2 clock inputs that are muxed dependin

Question

This small design has 2 clock inputs that are muxed depending on external signal <https github com GuillemCabo ASIC watch blob 2abd377cc5383e411fc9bbb33b881d98d1eaee78 hdl watch hhmm v>

Ahmed Ghazy · Answer

What s the internal clk net called tho

Matt Venn · Answer

clk crystal i

Ahmed Ghazy · Answer

Is that what shows up being connected to the CLK pins of cells in the gate level netlist

Matt Venn · Answer

It s like < tnt> says That design uses a lot of different clocks all going to relatively few cells

Matt Venn · Answer

the clock is divided down to get lots of different slow clocks

tnt · Answer

Basically this clock design generate a 1 second clock a 1 minute clock a 1hour clock etc all through clock dividers so you have a bunch of different nets clocking FFs

Ahmed Ghazy · Answer

< Matt Venn> You should be able to set multiple values for `CLOCK NET` e g ` clk crystal i clk2s int clk1m int ` I would check the actual gate level netlist to make sure that these nets didn t get renamed by yosys though

Matt Aamold · Answer

I ve been having this same issue so I m glad this was brought up Probably a noob question but where in the output directories can I find the gate level netlist

Matt Aamold · Answer

Is it runs lt design gt results lt design gt synthesis v