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#openlane
Title
# openlane
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Mariam Zanaty

04/27/2021, 8:23 AM
Hello everyone, There is something I wanted to ask about if it happens with someone before. on checking on the drcs on magic inside openroad on typing
run_magic_drc
i found that there is no violations but when I open magic gui I found a huge number of drc violations. so if this happens with someone before, what I have to do in this case?
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Amro Tork

04/27/2021, 8:05 PM
@Amr Gouhar @Tim Edwards @Ahmed Ghazy @Manar Abdelatty, Could you please help with that?
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Tim Edwards

04/27/2021, 8:15 PM
@Mariam Zanaty: What kind of errors are you seeing in the layout view?
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Mariam Zanaty

04/28/2021, 4:12 AM
@Tim Edwards
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Tim Edwards

04/28/2021, 1:26 PM
@Mariam Zanaty: These look like errors related to SRAM. SRAM should be viewed only as an abstract view, because it is full of special DRC rule exceptions that magic cannot capture.
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Mariam Zanaty

04/28/2021, 1:36 PM
@Tim Edwards Great, I have another question please, in my design I disable cell sizing and buffering however I capture lots of decapping, filler and buffer cells of large sizes, I think may be I modified in the layout by mistake. This window appears to me, I think I've to select flush to restore what is stored on the disk but I don't know how to make this window appear again. I've 71 modified cells in my layout so I think it's difficult to change this one by one on the console. So I'm asking from where I can get this window back again? if you could help please.
Screenshot from 2021-04-28 14-26-04.png
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Tim Edwards

04/28/2021, 1:39 PM
@Mariam Zanaty: This window appears when you do "writeall" (no arguments).
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Mariam Zanaty

04/28/2021, 1:55 PM
@Tim Edwards Great, thank you.
@Tim Edwards I've something more if you could give me your opinion please, I found that the problem was from the very beginning from the synthesis stage, as I mention I disable buffering and sizing in my config.tcl however I found the generated gate level netlist after synthesis contains buffering cells and of large sizes(1 & 2) what do you think I've to do in this case?
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Tim Edwards

04/28/2021, 3:21 PM
@Mariam Zanaty: I'm not the expert on using openlane. You should ask @Manar Abdelatty.
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Mariam Zanaty

04/28/2021, 3:22 PM
@Tim Edwards okay thank you so much.
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Amro Tork

04/28/2021, 3:23 PM
@Manar Abdelatty Could you please help?
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Mariam Zanaty

04/28/2021, 3:23 PM
@Manar Abdelatty could you please help me in this?
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Manar Abdelatty

04/28/2021, 3:29 PM
@Mariam Zanaty Openlane always runs yosys
ins_buf
command to get rid of assignment statements. The
SYNTH_BUFFERING
only disables abc buffering. So, if you have assign statements I would expect for the design to have buffer cells. Is this case with your design ?
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Mariam Zanaty

04/28/2021, 3:39 PM
@Manar Abdelatty Yes, I only changed in SYNTH_BUFFERING variable's value. but, I don't understand how to disable Yosys buffering, do you mean I've to change in the tcl script?
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Manar Abdelatty

04/28/2021, 3:48 PM
@Mariam Zanaty If you comment this line here https://github.com/efabless/openlane/blob/master/scripts/synth.tcl#L341, it will disable inserting buffer cells for assign statements. But, this will make the flow fail as openroad doesn't work properly with assign statements in the gate level netlist. What I am trying to say is that even if you disable buffering by setting
SYNTH_BUFFERING
to zero, the netlist could still have buffer cells because of the
ins_buf
command.
SYNTH_BUFFERING
only disables the cell buffering that abc does.
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Mariam Zanaty

04/28/2021, 4:15 PM
@Manar Abdelatty Yes, I got your point thank you, but there is other thing please, as you see I want to control cell sizing as much as possible, what happens is that I detect a huge difference after placement and after routing and that's I think the main issue I have. first screenshoot is after placement and the second one after routing. you'll be able to see that there is a de-cap cells of sizes 8 and even 12 was inserted. I don't know how. If you could help please.
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Manar Abdelatty

04/28/2021, 4:22 PM
@Mariam Zanaty decap cells are physical only cells and they get inserted into the free space you have in the floorplan. So, decap 8 and 12 must have been there before routing. If you want to control resizing because of space, you could consider setting the cell pad to zero. This would give you extra space without decreasing the core utilization.
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Mariam Zanaty

04/28/2021, 6:09 PM
@Manar Abdelatty Yes, I understood this but honestly, I capture these screen-shoots from the same corner of the layout, also I changed the cell pad and I still have the same errors, but they decreased a little bit. Something else if you could give me your opinion please, when I ran
run_magic_spice_export
I got some errors, as routing over obstructions, also when I open magic I found a huge number of drcs, so what do you think I can manipulate in this case?
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Manar Abdelatty

04/28/2021, 9:40 PM
@Mariam Zanaty I think the left image might have been captured before the decap insertion. The final def written after placement should be under
results/placement
. What kind of errors are you having exactly after changing the cell pad ?
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Mariam Zanaty

04/30/2021, 7:32 PM
@Manar Abdelatty Thank you for the supportive initiative, but I manage to solve the errors I had. But, in the same run I got LVS errors and they decreased when I extract from the gds not from lef/def. Now I still have 9 LVS errors and a huge drcs, that I found that they are increasing with the decreasing of the core area but and on the other hand when I increase the core area I found other errors as routing over obstructions appear, I think tap cells placement may be a reason behind this as by default the tap cells columns distant from each other by a certain value. So the more I restrict the core area the less tapcells that are being inserted. I'm thinking so as the tap and decap cells are the only variables in my design. So now I'm asking if you could give me your opinion in this case & what can I manipulate in for LVS and drcs errors solving?
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