Getting an error at Step Index 9 - currently runni...
# openlane
Getting an error at Step Index 9 - currently running the flow from the
repo. Where can I adjust macro placements or PDN offsets/pitches? I have a fully standard cell digital design.
@Eldrick Saleh Millares You can find the PDN pitch variables documented here . On another note, I think vssa1 is an analog ground. So, if you have a fully digital project, why are you using it ?
Thanks Manar! Great question - I was trying to bootstrap our flow from and was not sure what to remove / modify for our digital project. How should I go about removing / disabling the analog features?
@Eldrick Saleh Millares For the user_project_wrapper, you need to draw the four power domains even if you aren't using one of them. This core ring config and power domains are defined in the fixed_wrapper_cfg.tcl which shouldn't be changed. If you have a macro inside your design that is fully digital, you can only draw the digital domain (vccd1/vssd1). In the user_proj_example, we have the four power domains drawn, but this isn't a must. You will need to reflect the power connection in the verilog as well (for macros only, standard cells are automatically connected to vccd1). You can refer to to know more about this.
@Manar Abdelatty We're instantiating the top level of our design in
, which is fully digital. My understanding then is that we should: 1 Comment out the non-digital domain power signals in
within the
such that:
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`ifdef USE_POWER_PINS                                
    // inout vdda1,     // User area 1 3.3V supply   
    // inout vdda2,     // User area 2 3.3V supply   
    // inout vssa1,     // User area 1 analog ground 
    // inout vssa2,     // User area 2 analog ground 
    inout vccd1,        // User area 1 1.8V supply   
    // inout vccd2,        // User area 2 1.8v supply   
    inout vssd1,        // User area 1 digital ground
    // inout vssd2,        // User area 2 digital ground
2. Only have
within the openlane
script such that:
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# set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
# set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(VDD_NETS) [list {vccd1}]                          
set ::env(GND_NETS) [list {vssd1}]
Did I understand that correctly? Thank you again for the help
@Eldrick Saleh Millares Yes, correct. You can comment the unused power domains for any macros you have inside the wrapper.
🙌 1
Doing so allowed me to complete to the end of the flow yesterday without errors! Thank you immensely for the help. Now on to removing some of the antenna violations, but first a few RTL revisions 🙂