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#openlane
Title
# openlane
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Eldrick Saleh Millares

05/12/2021, 10:02 PM
Getting an error at Step Index 9 - currently running the flow from the
caravel_user_project
repo. Where can I adjust macro placements or PDN offsets/pitches? I have a fully standard cell digital design.
m

Manar Abdelatty

05/12/2021, 11:00 PM
@Eldrick Saleh Millares You can find the PDN pitch variables documented here https://github.com/efabless/openlane/tree/master/configuration#floorplanning . On another note, I think vssa1 is an analog ground. So, if you have a fully digital project, why are you using it ?
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Eldrick Saleh Millares

05/12/2021, 11:03 PM
Thanks Manar! Great question - I was trying to bootstrap our flow from https://github.com/efabless/caravel_user_project and was not sure what to remove / modify for our digital project. How should I go about removing / disabling the analog features?
m

Manar Abdelatty

05/12/2021, 11:38 PM
@Eldrick Saleh Millares For the user_project_wrapper, you need to draw the four power domains even if you aren't using one of them. This core ring config and power domains are defined in the fixed_wrapper_cfg.tcl which shouldn't be changed. If you have a macro inside your design that is fully digital, you can only draw the digital domain (vccd1/vssd1). In the user_proj_example, we have the four power domains drawn, but this isn't a must. You will need to reflect the power connection in the verilog as well (for macros only, standard cells are automatically connected to vccd1). You can refer to https://github.com/efabless/openlane/blob/478c59c9077f924096e608a8e5a26cfae9979001/docs/source/advanced_power_grid_control.md to know more about this.
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Eldrick Saleh Millares

05/13/2021, 8:22 PM
@Manar Abdelatty We're instantiating the top level of our design in
user_proj_example
, which is fully digital. My understanding then is that we should: 1 Comment out the non-digital domain power signals in
user_proj_example.v
within the
USE_POWER_PINS
ifdef
such that:
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`ifdef USE_POWER_PINS                                
    // inout vdda1,     // User area 1 3.3V supply   
    // inout vdda2,     // User area 2 3.3V supply   
    // inout vssa1,     // User area 1 analog ground 
    // inout vssa2,     // User area 2 analog ground 
    inout vccd1,        // User area 1 1.8V supply   
    // inout vccd2,        // User area 2 1.8v supply   
    inout vssd1,        // User area 1 digital ground
    // inout vssd2,        // User area 2 digital ground
`endif
2. Only have
vccd1/vssd1
within the openlane
config.tcl
script such that:
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# set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
# set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(VDD_NETS) [list {vccd1}]                          
set ::env(GND_NETS) [list {vssd1}]
Did I understand that correctly? Thank you again for the help
m

Manar Abdelatty

05/14/2021, 12:01 PM
@Eldrick Saleh Millares Yes, correct. You can comment the unused power domains for any macros you have inside the wrapper.
🙌 1
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Eldrick Saleh Millares

05/14/2021, 3:53 PM
Doing so allowed me to complete to the end of the flow yesterday without errors! Thank you immensely for the help. Now on to removing some of the antenna violations, but first a few RTL revisions 🙂
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